nv-tegra-mirror/linux-nvgpu
1
0
Fork 0
mirror of git://nv-tegra.nvidia.com/linux-nvgpu.git synced 2025-12-24 02:22:34 +03:00
Code Issues Packages Projects Releases Wiki Activity

gpu: nvgpu: Add GM20b pll registers error dump

Browse Source 
Change-Id: I67fe2c4cbab1d43670131d95bbea732e932c0910
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/494164
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
This commit is contained in:
Alex Frid
2014-08-29 18:19:54 -07:00
committed by Dan Willemsen
parent 59299f007a
commit 02d0e8d574
1 changed files with 21 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

21
drivers/gpu/nvgpu/gm20b/clk_gm20b.c
View File

@@ -46,6 +46,26 @@ static struct pll_parms gpc_pll_params = {
static int clk_gm20b_debugfs_init(struct gk20a *g);
#endif
#define DUMP_REG(addr_func) \
do { \
addr = trim_sys_##addr_func##_r(); \
data = gk20a_readl(g, addr); \
pr_info(#addr_func "[0x%x] = 0x%x\n", addr, data); \
} while (0)
static void dump_gpc_pll(struct gk20a *g, struct pll *gpll, u32 last_cfg)
{
u32 addr, data;
pr_info("**** GPCPLL DUMP ****");
pr_info("gpcpll s/w M=%u N=%u P=%u\n", gpll->M, gpll->N, gpll->PL);
pr_info("gpcpll_cfg_last = 0x%x\n", last_cfg);
DUMP_REG(gpcpll_cfg);
DUMP_REG(gpcpll_coeff);
DUMP_REG(sel_vco);
pr_info("\n");
}
/* 1:1 match between post divider settings and divisor value */
static inline u32 pl_to_div(u32 pl)
{
@@ -344,6 +364,7 @@ static int clk_lock_gpc_pll_under_bypass(struct gk20a *g, struct pll *gpll)
} while (--timeout > 0);
/* PLL is messed up. What can we do here? */
dump_gpc_pll(g, gpll, cfg);
BUG();
return -EBUSY;