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gpu: nvgpu: separate API to get failing engine data

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In gk20a_fifo_handle_sched_error(), we currently have a sequence
to identify failing engine (stuck on context switch) and
corresponding failing channel with its type

Separate out this sequence in new API
gk20a_fifo_get_failing_engine_data() so that it can be
reused from else where too

Bug 200133289

Change-Id: I3cef395170cf8990c014c7505c798fd6f2e37921
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/797070
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
This commit is contained in:
Deepak Nibade
2015-09-08 21:11:51 +05:30
committed by Terje Bergstrom
parent f6311b58b3
commit 0398e0751f
2 changed files with 31 additions and 12 deletions
Download Patch File Download Diff File Expand all files Collapse all files

41
drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
View File

@@ -1357,16 +1357,13 @@ int gk20a_fifo_force_reset_ch(struct channel_gk20a *ch, bool verbose)
return 0;
}
static bool gk20a_fifo_handle_sched_error(struct gk20a *g)
u32 gk20a_fifo_get_failing_engine_data(struct gk20a *g,
int *__id, bool *__is_tsg)
{
u32 sched_error;
u32 engine_id;
u32 engine_id = -1;
int id = -1;
bool non_chid = false;
bool ret = false;
bool is_tsg = false;
u32 mailbox2;
/* read the scheduler error register */
sched_error = gk20a_readl(g, fifo_intr_sched_error_r());
for (engine_id = 0; engine_id < g->fifo.max_engines; engine_id++) {
u32 status = gk20a_readl(g, fifo_engine_status_r(engine_id));
@@ -1388,13 +1385,14 @@ static bool gk20a_fifo_handle_sched_error(struct gk20a *g)
if (!failing_engine)
continue;
if (ctx_status ==
fifo_engine_status_ctx_status_ctxsw_load_v()) {
fifo_engine_status_ctx_status_ctxsw_load_v()) {
id = fifo_engine_status_next_id_v(status);
non_chid = fifo_pbdma_status_id_type_v(status)
is_tsg = fifo_pbdma_status_id_type_v(status)
!= fifo_pbdma_status_id_type_chid_v();
} else if (ctx_status ==
fifo_engine_status_ctx_status_ctxsw_switch_v()) {
fifo_engine_status_ctx_status_ctxsw_switch_v()) {
mailbox2 = gk20a_readl(g, gr_fecs_ctxsw_mailbox_r(2));
if (mailbox2 & FECS_METHOD_WFI_RESTORE)
id = fifo_engine_status_next_id_v(status);
@@ -1406,6 +1404,25 @@ static bool gk20a_fifo_handle_sched_error(struct gk20a *g)
break;
}
*__id = id;
*__is_tsg = is_tsg;
return engine_id;
}
static bool gk20a_fifo_handle_sched_error(struct gk20a *g)
{
u32 sched_error;
u32 engine_id;
int id = -1;
bool is_tsg = false;
bool ret = false;
/* read the scheduler error register */
sched_error = gk20a_readl(g, fifo_intr_sched_error_r());
engine_id = gk20a_fifo_get_failing_engine_data(g, &id, &is_tsg);
/* could not find the engine - should never happen */
if (unlikely(engine_id >= g->fifo.max_engines)) {
gk20a_err(dev_from_gk20a(g), "fifo sched error : 0x%08x, failed to find engine\n",
@@ -1419,7 +1436,7 @@ static bool gk20a_fifo_handle_sched_error(struct gk20a *g)
struct fifo_gk20a *f = &g->fifo;
struct channel_gk20a *ch = &f->channel[id];
if (non_chid) {
if (is_tsg) {
gk20a_fifo_recover(g, BIT(engine_id), id, true,
true, true);
ret = true;
@@ -1453,7 +1470,7 @@ static bool gk20a_fifo_handle_sched_error(struct gk20a *g)
}
gk20a_err(dev_from_gk20a(g), "fifo sched error : 0x%08x, engine=%u, %s=%d",
sched_error, engine_id, non_chid ? "non-ch" : "ch", id);
sched_error, engine_id, is_tsg ? "tsg" : "ch", id);
err:
return ret;

2
drivers/gpu/nvgpu/gk20a/fifo_gk20a.h
View File

@@ -177,5 +177,7 @@ void fifo_gk20a_finish_mmu_fault_handling(struct gk20a *g,
int gk20a_fifo_wait_engine_idle(struct gk20a *g);
u32 gk20a_fifo_engine_interrupt_mask(struct gk20a *g);
u32 gk20a_fifo_get_pbdma_signature(struct gk20a *g);
u32 gk20a_fifo_get_failing_engine_data(struct gk20a *g,
int *__id, bool *__is_tsg);
#endif /*__GR_GK20A_H__*/