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gpu: nvgpu: Create CIC-mon and CIC-rm subunits

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common.cic unit is divided into common.cic.mon and common.cic.rm
based on rm and mon process split.

CIC-mon subunit includes the code which is utilized in critical
interrupt handling path like initialization, error detection and
error reporting path. CIC-rm subunit includes the code corresponding
to rest of interrupt handling(like collecting error debug data from
registers) and ISR status management (status of deferred interrupts).

Split the CIC APIs and data-members into above two subunits.

JIRA NVGPU-6899

Change-Id: I151b59105ff570607c4a62e974785e9c1323ef69
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2551897
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
tkudav
2021-06-30 15:45:08 +05:30
committed by mobile promotions
parent 8ccf9820ba
commit 0526e7eaa9
82 changed files with 934 additions and 733 deletions
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11
drivers/gpu/nvgpu/os/linux/pci.c
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@@ -24,7 +24,8 @@
#include <nvgpu/nvgpu_common.h>
#include <nvgpu/kmem.h>
#include <nvgpu/mc.h>
#include <nvgpu/cic.h>
#include <nvgpu/cic_mon.h>
#include <nvgpu/cic_rm.h>
#include <nvgpu/enabled.h>
#include <nvgpu/errata.h>
#include <nvgpu/nvlink_probe.h>
@@ -326,8 +327,8 @@ static struct pci_device_id nvgpu_pci_table[] = {
static irqreturn_t nvgpu_pci_isr(int irq, void *dev_id)
{
struct gk20a *g = dev_id;
u32 ret_stall = nvgpu_cic_intr_stall_isr(g);
u32 ret_nonstall = nvgpu_cic_intr_nonstall_isr(g);
u32 ret_stall = nvgpu_cic_mon_intr_stall_isr(g);
u32 ret_nonstall = nvgpu_cic_mon_intr_nonstall_isr(g);
#if defined(CONFIG_PCI_MSI)
/* Send MSI EOI */
@@ -347,8 +348,8 @@ static irqreturn_t nvgpu_pci_intr_thread(int irq, void *dev_id)
{
struct gk20a *g = dev_id;
nvgpu_cic_intr_stall_handle(g);
nvgpu_cic_intr_nonstall_handle(g);
nvgpu_cic_mon_intr_stall_handle(g);
nvgpu_cic_mon_intr_nonstall_handle(g);
return IRQ_HANDLED;
}