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gpu: nvgpu: Create CIC-mon and CIC-rm subunits

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common.cic unit is divided into common.cic.mon and common.cic.rm
based on rm and mon process split.

CIC-mon subunit includes the code which is utilized in critical
interrupt handling path like initialization, error detection and
error reporting path. CIC-rm subunit includes the code corresponding
to rest of interrupt handling(like collecting error debug data from
registers) and ISR status management (status of deferred interrupts).

Split the CIC APIs and data-members into above two subunits.

JIRA NVGPU-6899

Change-Id: I151b59105ff570607c4a62e974785e9c1323ef69
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2551897
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
tkudav
2021-06-30 15:45:08 +05:30
committed by mobile promotions
parent 8ccf9820ba
commit 0526e7eaa9
82 changed files with 934 additions and 733 deletions
Download Patch File Download Diff File Expand all files Collapse all files

31
arch/nvgpu-common.yaml
View File

@@ -1074,20 +1074,23 @@ grmgr:
cic:
owner: Tejal K
safe: yes
sources: [ common/cic/cic.c,
common/cic/cic_intr.c,
common/cic/ce_cic.c,
common/cic/ctxsw_cic.c,
common/cic/msg_cic.c,
common/cic/ecc_cic.c,
common/cic/host_cic.c,
common/cic/gr_cic.c,
common/cic/pri_cic.c,
common/cic/pmu_cic.c,
common/cic/mmu_cic.c,
common/cic/cic_priv.h,
include/nvgpu/gops/cic.h,
include/nvgpu/cic.h ]
sources: [ common/cic/mon/mon_init.c,
common/cic/mon/mon_lut.c,
common/cic/mon/mon_intr.c,
common/cic/mon/mon_ce.c,
common/cic/mon/mon_ctxsw.c,
common/cic/mon/mon_msg.c,
common/cic/mon/mon_ecc.c,
common/cic/mon/mon_host.c,
common/cic/mon/mon_gr.c,
common/cic/mon/mon_pri.c,
common/cic/mon/mon_pmu.c,
common/cic/mon/mon_mmu.c,
common/cic/mon/cic_mon_priv.h,
include/nvgpu/gops/cic_mon.h,
include/nvgpu/cic_mon.h,
common/cic/rm/rm_intr.c,
include/nvgpu/cic_rm.h ]
##
## HAL units. Currently they are under common but this needs to change.

6
arch/nvgpu-hal-new.yaml
View File

@@ -1032,9 +1032,9 @@ tpc:
cic:
safe: yes
owner: Tejal K
sources: [ hal/cic/cic_gv11b_fusa.c,
hal/cic/cic_lut_gv11b_fusa.c,
hal/cic/cic_gv11b.h ]
sources: [ hal/cic/mon/init_gv11b_fusa.c,
hal/cic/mon/lut_gv11b_fusa.c,
hal/cic/mon/cic_gv11b.h ]
grmgr:
safe: no

28
drivers/gpu/nvgpu/Makefile
View File

@@ -308,17 +308,19 @@ nvgpu-y += \
common/clk_arb/clk_arb_gp10b.o \
common/rc/rc.o \
common/grmgr/grmgr.o \
common/cic/cic.o \
common/cic/cic_intr.o \
common/cic/ce_cic.o \
common/cic/ctxsw_cic.o \
common/cic/ecc_cic.o \
common/cic/host_cic.o \
common/cic/gr_cic.o \
common/cic/pri_cic.o \
common/cic/pmu_cic.o \
common/cic/mmu_cic.o \
common/cic/msg_cic.o \
common/cic/mon/mon_init.o \
common/cic/mon/mon_lut.o \
common/cic/mon/mon_intr.o \
common/cic/mon/mon_ce.o \
common/cic/mon/mon_ctxsw.o \
common/cic/mon/mon_msg.o \
common/cic/mon/mon_ecc.o \
common/cic/mon/mon_host.o \
common/cic/mon/mon_gr.o \
common/cic/mon/mon_pri.o \
common/cic/mon/mon_pmu.o \
common/cic/mon/mon_mmu.o \
common/cic/rm/rm_intr.o \
hal/bus/bus_gk20a.o \
hal/class/class_gm20b.o \
hal/class/class_gp10b.o \
@@ -392,8 +394,8 @@ nvgpu-y += \
hal/top/top_gp10b.o \
hal/tpc/tpc_gv11b.o \
hal/priv_ring/priv_ring_gv11b.o \
hal/cic/cic_gv11b_fusa.o \
hal/cic/cic_lut_gv11b_fusa.o
hal/cic/mon/init_gv11b_fusa.o \
hal/cic/mon/lut_gv11b_fusa.o
# Linux specific parts of nvgpu.
nvgpu-y += \

28
drivers/gpu/nvgpu/Makefile.sources
View File

@@ -155,17 +155,19 @@ srcs += common/device.c \
common/rc/rc.c \
common/ce/ce.c \
common/grmgr/grmgr.c \
common/cic/cic.c \
common/cic/cic_intr.c \
common/cic/ce_cic.c \
common/cic/ctxsw_cic.c \
common/cic/ecc_cic.c \
common/cic/host_cic.c \
common/cic/gr_cic.c \
common/cic/pri_cic.c \
common/cic/pmu_cic.c \
common/cic/mmu_cic.c \
common/cic/msg_cic.c \
common/cic/mon/mon_init.c \
common/cic/mon/mon_lut.c \
common/cic/mon/mon_intr.c \
common/cic/mon/mon_ce.c \
common/cic/mon/mon_ctxsw.c \
common/cic/mon/mon_msg.c \
common/cic/mon/mon_ecc.c \
common/cic/mon/mon_host.c \
common/cic/mon/mon_gr.c \
common/cic/mon/mon_pri.c \
common/cic/mon/mon_pmu.c \
common/cic/mon/mon_mmu.c \
common/cic/rm/rm_intr.c \
hal/init/hal_gv11b.c \
hal/init/hal_gv11b_litter.c \
hal/init/hal_init.c \
@@ -261,8 +263,8 @@ srcs += hal/mm/mm_gv11b_fusa.c \
hal/therm/therm_gv11b_fusa.c \
hal/top/top_gm20b_fusa.c \
hal/top/top_gv11b_fusa.c \
hal/cic/cic_gv11b_fusa.c \
hal/cic/cic_lut_gv11b_fusa.c
hal/cic/mon/init_gv11b_fusa.c \
hal/cic/mon/lut_gv11b_fusa.c
# Source files below are not guaranteed to be functionaly safe (FuSa) and are
# only included in the normal build.

6
drivers/gpu/nvgpu/common/ce/ce.c
View File

@@ -26,7 +26,7 @@
#include <nvgpu/device.h>
#include <nvgpu/ce.h>
#include <nvgpu/power_features/cg.h>
#include <nvgpu/cic.h>
#include <nvgpu/cic_mon.h>
#include <nvgpu/mc.h>
int nvgpu_ce_init_support(struct gk20a *g)
@@ -64,8 +64,8 @@ int nvgpu_ce_init_support(struct gk20a *g)
}
/** Enable interrupts at MC level */
nvgpu_cic_intr_stall_unit_config(g, NVGPU_CIC_INTR_UNIT_CE, NVGPU_CIC_INTR_ENABLE);
nvgpu_cic_intr_nonstall_unit_config(g, NVGPU_CIC_INTR_UNIT_CE, NVGPU_CIC_INTR_ENABLE);
nvgpu_cic_mon_intr_stall_unit_config(g, NVGPU_CIC_INTR_UNIT_CE, NVGPU_CIC_INTR_ENABLE);
nvgpu_cic_mon_intr_nonstall_unit_config(g, NVGPU_CIC_INTR_UNIT_CE, NVGPU_CIC_INTR_ENABLE);
return 0;
}

230
drivers/gpu/nvgpu/common/cic/cic.c
View File

@@ -1,230 +0,0 @@
/*
* Copyright (c) 2021, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#include <nvgpu/gk20a.h>
#include <nvgpu/kmem.h>
#include <nvgpu/lock.h>
#include <nvgpu/log.h>
#include <nvgpu/cic.h>
#include <nvgpu/nvgpu_err_info.h>
#include "cic_priv.h"
int nvgpu_cic_init_common(struct gk20a *g)
{
struct nvgpu_cic *cic;
int err = 0;
if (g->cic != NULL) {
cic_dbg(g, "CIC unit already initialized");
return 0;
}
cic = nvgpu_kzalloc(g, sizeof(*cic));
if (cic == NULL) {
nvgpu_err(g, "Failed to allocate memory "
"for struct nvgpu_cic");
return -ENOMEM;
}
if (g->ops.cic.init != NULL) {
err = g->ops.cic.init(g, cic);
if (err != 0) {
nvgpu_err(g, "CIC chip specific "
"initialization failed.");
goto cleanup;
}
} else {
cic->err_lut = NULL;
cic->num_hw_modules = 0;
}
g->cic = cic;
cic_dbg(g, "CIC unit initialization done.");
return 0;
cleanup:
if (cic != NULL) {
nvgpu_kfree(g, cic);
}
return err;
}
int nvgpu_cic_deinit_common(struct gk20a *g)
{
struct nvgpu_cic *cic;
cic = g->cic;
if (cic == NULL) {
cic_dbg(g, "CIC unit already deinitialized");
return 0;
}
cic->err_lut = NULL;
cic->num_hw_modules = 0;
nvgpu_kfree(g, cic);
g->cic = NULL;
return 0;
}
int nvgpu_cic_check_hw_unit_id(struct gk20a *g, u32 hw_unit_id)
{
if (g->cic == NULL) {
nvgpu_err(g, "CIC is not initialized");
return -EINVAL;
}
if (g->cic->num_hw_modules == 0U) {
cic_dbg(g, "LUT not initialized.");
return -EINVAL;
}
if (hw_unit_id >= g->cic->num_hw_modules) {
cic_dbg(g, "Invalid input HW unit ID.");
return -EINVAL;
}
return 0;
}
int nvgpu_cic_check_err_id(struct gk20a *g, u32 hw_unit_id,
u32 err_id)
{
int err = 0;
if ((g->cic == NULL) || (g->cic->err_lut == NULL)) {
cic_dbg(g, "CIC/LUT not initialized.");
return -EINVAL;
}
err = nvgpu_cic_check_hw_unit_id(g, hw_unit_id);
if (err != 0) {
return err;
}
if (err_id >= g->cic->err_lut[hw_unit_id].num_errs) {
err = -EINVAL;
}
return err;
}
int nvgpu_cic_get_err_desc(struct gk20a *g, u32 hw_unit_id,
u32 err_id, struct nvgpu_err_desc **err_desc)
{
int err = 0;
/* if (g->cic != NULL) and (g->cic->err_lut != NULL) check
* can be skipped here as it checked as part of
* nvgpu_cic_check_err_id() called below.
*/
err = nvgpu_cic_check_err_id(g, hw_unit_id, err_id);
if (err != 0) {
return err;
}
*err_desc = &(g->cic->err_lut[hw_unit_id].errs[err_id]);
return err;
}
int nvgpu_cic_get_num_hw_modules(struct gk20a *g)
{
if (g->cic == NULL) {
nvgpu_err(g, "CIC is not initialized");
return -EINVAL;
}
return g->cic->num_hw_modules;
}
#if defined(CONFIG_NVGPU_NON_FUSA)
void nvgpu_cic_intr_unit_vectorid_init(struct gk20a *g, u32 unit, u32 *vectorid,
u32 num_entries)
{
unsigned long flags = 0;
u32 i = 0U;
struct nvgpu_intr_unit_info *intr_unit_info;
nvgpu_assert(num_entries <= NVGPU_CIC_INTR_VECTORID_SIZE_MAX);
nvgpu_log(g, gpu_dbg_intr, "UNIT=%d, nvecs=%d", unit, num_entries);
intr_unit_info = g->mc.intr_unit_info;
nvgpu_spinlock_irqsave(&g->mc.intr_lock, flags);
if (intr_unit_info[unit].valid == false) {
for (i = 0U; i < num_entries; i++) {
nvgpu_log(g, gpu_dbg_intr, " vec[%d] = %d", i,
*(vectorid + i));
intr_unit_info[unit].vectorid[i] = *(vectorid + i);
}
intr_unit_info[unit].vectorid_size = num_entries;
}
nvgpu_spinunlock_irqrestore(&g->mc.intr_lock, flags);
}
bool nvgpu_cic_intr_is_unit_info_valid(struct gk20a *g, u32 unit)
{
struct nvgpu_intr_unit_info *intr_unit_info;
bool info_valid = false;
if (unit >= NVGPU_CIC_INTR_UNIT_MAX) {
nvgpu_err(g, "invalid unit(%d)", unit);
return false;
}
intr_unit_info = g->mc.intr_unit_info;
if (intr_unit_info[unit].valid == true) {
info_valid = true;
}
return info_valid;
}
bool nvgpu_cic_intr_get_unit_info(struct gk20a *g, u32 unit, u32 *subtree,
u64 *subtree_mask)
{
if (unit >= NVGPU_CIC_INTR_UNIT_MAX) {
nvgpu_err(g, "invalid unit(%d)", unit);
return false;
}
if (nvgpu_cic_intr_is_unit_info_valid(g, unit) != true) {
if (g->ops.mc.intr_get_unit_info(g, unit) != true) {
nvgpu_err(g, "failed to fetch info for unit(%d)", unit);
return false;
}
}
*subtree = g->mc.intr_unit_info[unit].subtree;
*subtree_mask = g->mc.intr_unit_info[unit].subtree_mask;
nvgpu_log(g, gpu_dbg_intr, "subtree(%d) subtree_mask(%llx)",
*subtree, *subtree_mask);
return true;
}
#endif

17
drivers/gpu/nvgpu/common/cic/cic_priv.h → drivers/gpu/nvgpu/common/cic/mon/cic_mon_priv.h
View File

@@ -20,36 +20,29 @@
* DEALINGS IN THE SOFTWARE.
*/
#ifndef CIC_PRIV_H
#define CIC_PRIV_H
#ifndef CIC_MON_PRIV_H
#define CIC_MON_PRIV_H
#include <nvgpu/types.h>
#include <nvgpu/lock.h>
struct gk20a;
struct nvgpu_err_hw_module;
struct nvgpu_err_msg;
struct gpu_err_header;
/*
* @file
*
* Declare CIC's private structure to store error-policy LUT and
* other data and ops needed during error reporting.
*/
#define ERR_INJECT_TEST_PATTERN 0xA5
/*
* This struct contains members related to error-policy look-up table,
* number of units reporting errors.
*/
struct nvgpu_cic {
struct nvgpu_cic_mon {
/** Pointer for error look-up table. */
struct nvgpu_err_hw_module *err_lut;
/** Total number of GPU HW modules considered in CIC. */
u32 num_hw_modules;
};
/**
@@ -288,4 +281,4 @@ void nvgpu_init_ctxsw_err_msg(struct nvgpu_err_msg *msg);
*/
void nvgpu_init_mmu_err_msg(struct nvgpu_err_msg *msg);
#endif /* CIC_PRIV_H */
#endif /* CIC_MON_PRIV_H */

12
drivers/gpu/nvgpu/common/cic/ce_cic.c → drivers/gpu/nvgpu/common/cic/mon/mon_ce.c
View File

@@ -24,9 +24,9 @@
#include <nvgpu/nvgpu_init.h>
#include <nvgpu/nvgpu_err.h>
#include <nvgpu/nvgpu_err_info.h>
#include <nvgpu/cic.h>
#include <nvgpu/cic_mon.h>
#include "cic_priv.h"
#include "cic_mon_priv.h"
void nvgpu_report_ce_err(struct gk20a *g, u32 hw_unit,
u32 inst, u32 err_id, u32 intr_info)
@@ -35,7 +35,7 @@ void nvgpu_report_ce_err(struct gk20a *g, u32 hw_unit,
struct nvgpu_err_desc *err_desc = NULL;
struct nvgpu_err_msg err_pkt;
if (g->ops.cic.report_err == NULL) {
if (g->ops.cic_mon.report_err == NULL) {
cic_dbg(g, "CIC does not support reporting error "
"to safety services");
return;
@@ -47,7 +47,7 @@ void nvgpu_report_ce_err(struct gk20a *g, u32 hw_unit,
goto handle_report_failure;
}
err = nvgpu_cic_get_err_desc(g, hw_unit, err_id, &err_desc);
err = nvgpu_cic_mon_get_err_desc(g, hw_unit, err_id, &err_desc);
if (err != 0) {
nvgpu_err(g, "Failed to get err_desc for "
"err_id (%u) for hw module (%u)",
@@ -69,8 +69,8 @@ void nvgpu_report_ce_err(struct gk20a *g, u32 hw_unit,
err_pkt.err_size = nvgpu_safe_cast_u64_to_u8(
sizeof(err_pkt.err_info.ce_info));
if (g->ops.cic.report_err != NULL) {
err = g->ops.cic.report_err(g, (void *)&err_pkt,
if (g->ops.cic_mon.report_err != NULL) {
err = g->ops.cic_mon.report_err(g, (void *)&err_pkt,
sizeof(err_pkt), err_desc->is_critical);
if (err != 0) {
nvgpu_err(g, "Failed to report CE error: "

12
drivers/gpu/nvgpu/common/cic/ctxsw_cic.c → drivers/gpu/nvgpu/common/cic/mon/mon_ctxsw.c
View File

@@ -24,9 +24,9 @@
#include <nvgpu/nvgpu_init.h>
#include <nvgpu/nvgpu_err.h>
#include <nvgpu/nvgpu_err_info.h>
#include <nvgpu/cic.h>
#include <nvgpu/cic_mon.h>
#include "cic_priv.h"
#include "cic_mon_priv.h"
void nvgpu_report_ctxsw_err(struct gk20a *g, u32 hw_unit, u32 err_id,
void *data)
@@ -37,7 +37,7 @@ void nvgpu_report_ctxsw_err(struct gk20a *g, u32 hw_unit, u32 err_id,
u32 inst = 0;
struct ctxsw_err_info *err_info = (struct ctxsw_err_info *)data;
if (g->ops.cic.report_err == NULL) {
if (g->ops.cic_mon.report_err == NULL) {
cic_dbg(g, "CIC does not support reporting error "
"to safety services");
return;
@@ -49,7 +49,7 @@ void nvgpu_report_ctxsw_err(struct gk20a *g, u32 hw_unit, u32 err_id,
goto handle_report_failure;
}
err = nvgpu_cic_get_err_desc(g, hw_unit, err_id, &err_desc);
err = nvgpu_cic_mon_get_err_desc(g, hw_unit, err_id, &err_desc);
if (err != 0) {
nvgpu_err(g, "Failed to get err_desc for"
" err_id (%u) for hw module (%u)",
@@ -71,8 +71,8 @@ void nvgpu_report_ctxsw_err(struct gk20a *g, u32 hw_unit, u32 err_id,
err_pkt.err_size = nvgpu_safe_cast_u64_to_u8(
sizeof(err_pkt.err_info.ctxsw_info));
if (g->ops.cic.report_err != NULL) {
err = g->ops.cic.report_err(g, (void *)&err_pkt,
if (g->ops.cic_mon.report_err != NULL) {
err = g->ops.cic_mon.report_err(g, (void *)&err_pkt,
sizeof(err_pkt), err_desc->is_critical);
if (err != 0) {
nvgpu_err(g, "Failed to report CTXSW error: "

12
drivers/gpu/nvgpu/common/cic/ecc_cic.c → drivers/gpu/nvgpu/common/cic/mon/mon_ecc.c
View File

@@ -24,9 +24,9 @@
#include <nvgpu/nvgpu_init.h>
#include <nvgpu/nvgpu_err.h>
#include <nvgpu/nvgpu_err_info.h>
#include <nvgpu/cic.h>
#include <nvgpu/cic_mon.h>
#include "cic_priv.h"
#include "cic_mon_priv.h"
void nvgpu_report_ecc_err(struct gk20a *g, u32 hw_unit, u32 inst,
u32 err_id, u64 err_addr, u64 err_count)
@@ -35,13 +35,13 @@ void nvgpu_report_ecc_err(struct gk20a *g, u32 hw_unit, u32 inst,
struct nvgpu_err_desc *err_desc = NULL;
struct nvgpu_err_msg err_pkt;
if (g->ops.cic.report_err == NULL) {
if (g->ops.cic_mon.report_err == NULL) {
cic_dbg(g, "CIC does not support reporting error "
"to safety services");
return;
}
err = nvgpu_cic_get_err_desc(g, hw_unit, err_id, &err_desc);
err = nvgpu_cic_mon_get_err_desc(g, hw_unit, err_id, &err_desc);
if (err != 0) {
nvgpu_err(g, "Failed to get err_desc for "
"err_id (%u) for hw module (%u)",
@@ -60,8 +60,8 @@ void nvgpu_report_ecc_err(struct gk20a *g, u32 hw_unit, u32 inst,
err_pkt.err_size = nvgpu_safe_cast_u64_to_u8(
sizeof(err_pkt.err_info.ecc_info));
if (g->ops.cic.report_err != NULL) {
err = g->ops.cic.report_err(g, (void *)&err_pkt,
if (g->ops.cic_mon.report_err != NULL) {
err = g->ops.cic_mon.report_err(g, (void *)&err_pkt,
sizeof(err_pkt), err_desc->is_critical);
if (err != 0) {
nvgpu_err(g, "Failed to report ECC error: hw_unit=%u, inst=%u, "

12
drivers/gpu/nvgpu/common/cic/gr_cic.c → drivers/gpu/nvgpu/common/cic/mon/mon_gr.c
View File

@@ -24,9 +24,9 @@
#include <nvgpu/nvgpu_init.h>
#include <nvgpu/nvgpu_err.h>
#include <nvgpu/nvgpu_err_info.h>
#include <nvgpu/cic.h>
#include <nvgpu/cic_mon.h>
#include "cic_priv.h"
#include "cic_mon_priv.h"
static void nvpgu_report_fill_err_info(u32 hw_unit,
struct nvgpu_err_msg *err_pkt, struct gr_err_info *err_info)
@@ -67,7 +67,7 @@ void nvgpu_report_gr_err(struct gk20a *g, u32 hw_unit, u32 inst,
struct nvgpu_err_desc *err_desc = NULL;
struct nvgpu_err_msg err_pkt;
if (g->ops.cic.report_err == NULL) {
if (g->ops.cic_mon.report_err == NULL) {
cic_dbg(g, "CIC does not support reporting error "
"to safety services");
return;
@@ -80,7 +80,7 @@ void nvgpu_report_gr_err(struct gk20a *g, u32 hw_unit, u32 inst,
goto handle_report_failure;
}
err = nvgpu_cic_get_err_desc(g, hw_unit, err_id, &err_desc);
err = nvgpu_cic_mon_get_err_desc(g, hw_unit, err_id, &err_desc);
if (err != 0) {
nvgpu_err(g, "Failed to get err_desc for "
"err_id (%u) for hw module (%u)",
@@ -98,8 +98,8 @@ void nvgpu_report_gr_err(struct gk20a *g, u32 hw_unit, u32 inst,
nvpgu_report_fill_err_info(hw_unit, &err_pkt, err_info);
err_pkt.err_size = nvgpu_safe_cast_u64_to_u8(sizeof(err_pkt.err_info));
if (g->ops.cic.report_err != NULL) {
err = g->ops.cic.report_err(g, (void *)&err_pkt,
if (g->ops.cic_mon.report_err != NULL) {
err = g->ops.cic_mon.report_err(g, (void *)&err_pkt,
sizeof(err_pkt), err_desc->is_critical);
if (err != 0) {
if (hw_unit == NVGPU_ERR_MODULE_SM) {

12
drivers/gpu/nvgpu/common/cic/host_cic.c → drivers/gpu/nvgpu/common/cic/mon/mon_host.c
View File

@@ -24,9 +24,9 @@
#include <nvgpu/nvgpu_init.h>
#include <nvgpu/nvgpu_err.h>
#include <nvgpu/nvgpu_err_info.h>
#include <nvgpu/cic.h>
#include <nvgpu/cic_mon.h>
#include "cic_priv.h"
#include "cic_mon_priv.h"
void nvgpu_report_host_err(struct gk20a *g, u32 hw_unit,
u32 inst, u32 err_id, u32 intr_info)
@@ -35,7 +35,7 @@ void nvgpu_report_host_err(struct gk20a *g, u32 hw_unit,
struct nvgpu_err_desc *err_desc = NULL;
struct nvgpu_err_msg err_pkt;
if (g->ops.cic.report_err == NULL) {
if (g->ops.cic_mon.report_err == NULL) {
cic_dbg(g, "CIC does not support reporting error "
"to safety services");
return;
@@ -47,7 +47,7 @@ void nvgpu_report_host_err(struct gk20a *g, u32 hw_unit,
goto handle_report_failure;
}
err = nvgpu_cic_get_err_desc(g, hw_unit, err_id, &err_desc);
err = nvgpu_cic_mon_get_err_desc(g, hw_unit, err_id, &err_desc);
if (err != 0) {
nvgpu_err(g, "Failed to get err_desc for "
"err_id (%u) for hw module (%u)",
@@ -69,8 +69,8 @@ void nvgpu_report_host_err(struct gk20a *g, u32 hw_unit,
err_pkt.err_size = nvgpu_safe_cast_u64_to_u8(
sizeof(err_pkt.err_info.host_info));
if (g->ops.cic.report_err != NULL) {
err = g->ops.cic.report_err(g, (void *)&err_pkt,
if (g->ops.cic_mon.report_err != NULL) {
err = g->ops.cic_mon.report_err(g, (void *)&err_pkt,
sizeof(err_pkt), err_desc->is_critical);
if (err != 0) {
nvgpu_err(g, "Failed to report HOST error: "

122
drivers/gpu/nvgpu/common/cic/mon/mon_init.c Normal file
View File

@@ -0,0 +1,122 @@
/*
* Copyright (c) 2021, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#include <nvgpu/gk20a.h>
#include <nvgpu/kmem.h>
#include <nvgpu/log.h>
#include <nvgpu/cic_mon.h>
#include "cic_mon_priv.h"
int nvgpu_cic_mon_setup(struct gk20a *g)
{
struct nvgpu_cic_mon *cic_mon;
int err = 0;
if (g->cic_mon != NULL) {
cic_dbg(g, "CIC_MON already initialized");
return 0;
}
cic_mon = nvgpu_kzalloc(g, sizeof(*cic_mon));
if (cic_mon == NULL) {
nvgpu_err(g, "Failed to allocate memory "
"for struct nvgpu_cic_mon");
return -ENOMEM;
}
g->cic_mon = cic_mon;
cic_dbg(g, "CIC_MON unit initialization done.");
return err;
}
int nvgpu_cic_mon_init_lut(struct gk20a *g)
{
struct nvgpu_cic_mon *cic_mon;
int err = 0;
cic_mon = g->cic_mon;
if (cic_mon == NULL) {
nvgpu_err(g, "CIC_MON setup pending");
return -EINVAL;
}
if (g->ops.cic_mon.init != NULL) {
err = g->ops.cic_mon.init(g, cic_mon);
if (err != 0) {
nvgpu_err(g, "CIC MON chip specific "
"initialization failed.");
goto cleanup;
}
} else {
cic_mon->err_lut = NULL;
cic_mon->num_hw_modules = 0;
}
return 0;
cleanup:
if (cic_mon != NULL) {
nvgpu_kfree(g, cic_mon);
g->cic_mon = NULL;
}
return err;
}
int nvgpu_cic_mon_remove(struct gk20a *g)
{
struct nvgpu_cic_mon *cic_mon;
cic_mon = g->cic_mon;
if (cic_mon == NULL) {
cic_dbg(g, "CIC_MON already removed");
return 0;
}
nvgpu_kfree(g, cic_mon);
g->cic_mon = NULL;
return 0;
}
int nvgpu_cic_mon_deinit_lut(struct gk20a *g)
{
struct nvgpu_cic_mon *cic_mon;
cic_mon = g->cic_mon;
if (cic_mon == NULL) {
cic_dbg(g, "CIC_MON and LUT removed");
return 0;
}
cic_mon->err_lut = NULL;
cic_mon->num_hw_modules = 0;
return 0;
}
int nvgpu_cic_mon_deinit(struct gk20a *g)
{
/** More deinit calls might get added here as CIC grows. */
return nvgpu_cic_mon_deinit_lut(g);
}

169
drivers/gpu/nvgpu/common/cic/cic_intr.c → drivers/gpu/nvgpu/common/cic/mon/mon_intr.c
View File

@@ -20,44 +20,16 @@
* DEALINGS IN THE SOFTWARE.
*/
#include <nvgpu/cic.h>
#include <nvgpu/cic_mon.h>
#include <nvgpu/cic_rm.h>
#include <nvgpu/gk20a.h>
#include <nvgpu/bug.h>
#include <nvgpu/nvgpu_init.h>
#include <nvgpu/trace.h>
int nvgpu_cic_wait_for_stall_interrupts(struct gk20a *g, u32 timeout)
{
/* wait until all stalling irqs are handled */
return NVGPU_COND_WAIT(&g->mc.sw_irq_stall_last_handled_cond,
nvgpu_atomic_read(&g->mc.sw_irq_stall_pending) == 0,
timeout);
}
#include "cic_mon_priv.h"
int nvgpu_cic_wait_for_nonstall_interrupts(struct gk20a *g, u32 timeout)
{
/* wait until all non-stalling irqs are handled */
return NVGPU_COND_WAIT(&g->mc.sw_irq_nonstall_last_handled_cond,
nvgpu_atomic_read(&g->mc.sw_irq_nonstall_pending) == 0,
timeout);
}
void nvgpu_cic_wait_for_deferred_interrupts(struct gk20a *g)
{
int ret;
ret = nvgpu_cic_wait_for_stall_interrupts(g, 0U);
if (ret != 0) {
nvgpu_err(g, "wait for stall interrupts failed %d", ret);
}
ret = nvgpu_cic_wait_for_nonstall_interrupts(g, 0U);
if (ret != 0) {
nvgpu_err(g, "wait for nonstall interrupts failed %d", ret);
}
}
void nvgpu_cic_intr_mask(struct gk20a *g)
void nvgpu_cic_mon_intr_mask(struct gk20a *g)
{
unsigned long flags = 0;
@@ -68,27 +40,7 @@ void nvgpu_cic_intr_mask(struct gk20a *g)
}
}
#ifdef CONFIG_NVGPU_NON_FUSA
void nvgpu_cic_log_pending_intrs(struct gk20a *g)
{
if (g->ops.mc.log_pending_intrs != NULL) {
g->ops.mc.log_pending_intrs(g);
}
}
void nvgpu_cic_intr_enable(struct gk20a *g)
{
unsigned long flags = 0;
if (g->ops.mc.intr_enable != NULL) {
nvgpu_spinlock_irqsave(&g->mc.intr_lock, flags);
g->ops.mc.intr_enable(g);
nvgpu_spinunlock_irqrestore(&g->mc.intr_lock, flags);
}
}
#endif
void nvgpu_cic_intr_stall_unit_config(struct gk20a *g, u32 unit, bool enable)
void nvgpu_cic_mon_intr_stall_unit_config(struct gk20a *g, u32 unit, bool enable)
{
unsigned long flags = 0;
@@ -97,7 +49,7 @@ void nvgpu_cic_intr_stall_unit_config(struct gk20a *g, u32 unit, bool enable)
nvgpu_spinunlock_irqrestore(&g->mc.intr_lock, flags);
}
void nvgpu_cic_intr_nonstall_unit_config(struct gk20a *g, u32 unit, bool enable)
void nvgpu_cic_mon_intr_nonstall_unit_config(struct gk20a *g, u32 unit, bool enable)
{
unsigned long flags = 0;
@@ -106,7 +58,7 @@ void nvgpu_cic_intr_nonstall_unit_config(struct gk20a *g, u32 unit, bool enable)
nvgpu_spinunlock_irqrestore(&g->mc.intr_lock, flags);
}
void nvgpu_cic_intr_stall_pause(struct gk20a *g)
void nvgpu_cic_mon_intr_stall_pause(struct gk20a *g)
{
unsigned long flags = 0;
@@ -115,7 +67,7 @@ void nvgpu_cic_intr_stall_pause(struct gk20a *g)
nvgpu_spinunlock_irqrestore(&g->mc.intr_lock, flags);
}
void nvgpu_cic_intr_stall_resume(struct gk20a *g)
void nvgpu_cic_mon_intr_stall_resume(struct gk20a *g)
{
unsigned long flags = 0;
@@ -124,7 +76,7 @@ void nvgpu_cic_intr_stall_resume(struct gk20a *g)
nvgpu_spinunlock_irqrestore(&g->mc.intr_lock, flags);
}
void nvgpu_cic_intr_nonstall_pause(struct gk20a *g)
void nvgpu_cic_mon_intr_nonstall_pause(struct gk20a *g)
{
unsigned long flags = 0;
@@ -133,7 +85,7 @@ void nvgpu_cic_intr_nonstall_pause(struct gk20a *g)
nvgpu_spinunlock_irqrestore(&g->mc.intr_lock, flags);
}
void nvgpu_cic_intr_nonstall_resume(struct gk20a *g)
void nvgpu_cic_mon_intr_nonstall_resume(struct gk20a *g)
{
unsigned long flags = 0;
@@ -142,7 +94,7 @@ void nvgpu_cic_intr_nonstall_resume(struct gk20a *g)
nvgpu_spinunlock_irqrestore(&g->mc.intr_lock, flags);
}
static void nvgpu_cic_intr_nonstall_work(struct gk20a *g, u32 work_ops)
static void nvgpu_cic_mon_intr_nonstall_work(struct gk20a *g, u32 work_ops)
{
bool semaphore_wakeup, post_events;
@@ -157,7 +109,7 @@ static void nvgpu_cic_intr_nonstall_work(struct gk20a *g, u32 work_ops)
}
}
u32 nvgpu_cic_intr_nonstall_isr(struct gk20a *g)
u32 nvgpu_cic_mon_intr_nonstall_isr(struct gk20a *g)
{
u32 non_stall_intr_val = 0U;
@@ -171,29 +123,30 @@ u32 nvgpu_cic_intr_nonstall_isr(struct gk20a *g)
return NVGPU_CIC_INTR_NONE;
}
nvgpu_cic_intr_nonstall_pause(g);
nvgpu_cic_mon_intr_nonstall_pause(g);
if (g->sw_quiesce_pending) {
return NVGPU_CIC_INTR_QUIESCE_PENDING;
}
nvgpu_atomic_set(&g->mc.sw_irq_nonstall_pending, 1);
return NVGPU_CIC_INTR_HANDLE;
}
void nvgpu_cic_intr_nonstall_handle(struct gk20a *g)
void nvgpu_cic_mon_intr_nonstall_handle(struct gk20a *g)
{
int err;
u32 nonstall_ops = 0;
nonstall_ops = g->ops.mc.isr_nonstall(g);
if (nonstall_ops != 0U) {
nvgpu_cic_intr_nonstall_work(g, nonstall_ops);
nvgpu_cic_mon_intr_nonstall_work(g, nonstall_ops);
}
/* sync handled irq counter before re-enabling interrupts */
nvgpu_atomic_set(&g->mc.sw_irq_nonstall_pending, 0);
nvgpu_cic_intr_nonstall_resume(g);
nvgpu_cic_mon_intr_nonstall_resume(g);
err = nvgpu_cond_broadcast(&g->mc.sw_irq_nonstall_last_handled_cond);
if (err != 0) {
@@ -201,7 +154,7 @@ void nvgpu_cic_intr_nonstall_handle(struct gk20a *g)
}
}
u32 nvgpu_cic_intr_stall_isr(struct gk20a *g)
u32 nvgpu_cic_mon_intr_stall_isr(struct gk20a *g)
{
u32 mc_intr_0 = 0U;
@@ -217,7 +170,7 @@ u32 nvgpu_cic_intr_stall_isr(struct gk20a *g)
return NVGPU_CIC_INTR_NONE;
}
nvgpu_cic_intr_stall_pause(g);
nvgpu_cic_mon_intr_stall_pause(g);
if (g->sw_quiesce_pending) {
return NVGPU_CIC_INTR_QUIESCE_PENDING;
@@ -230,7 +183,7 @@ u32 nvgpu_cic_intr_stall_isr(struct gk20a *g)
return NVGPU_CIC_INTR_HANDLE;
}
void nvgpu_cic_intr_stall_handle(struct gk20a *g)
void nvgpu_cic_mon_intr_stall_handle(struct gk20a *g)
{
int err;
@@ -242,10 +195,90 @@ void nvgpu_cic_intr_stall_handle(struct gk20a *g)
/* sync handled irq counter before re-enabling interrupts */
nvgpu_atomic_set(&g->mc.sw_irq_stall_pending, 0);
nvgpu_cic_intr_stall_resume(g);
nvgpu_cic_mon_intr_stall_resume(g);
err = nvgpu_cond_broadcast(&g->mc.sw_irq_stall_last_handled_cond);
if (err != 0) {
nvgpu_err(g, "nvgpu_cond_broadcast failed err=%d", err);
}
}
#ifdef CONFIG_NVGPU_NON_FUSA
void nvgpu_cic_mon_intr_enable(struct gk20a *g)
{
unsigned long flags = 0;
if (g->ops.mc.intr_enable != NULL) {
nvgpu_spinlock_irqsave(&g->mc.intr_lock, flags);
g->ops.mc.intr_enable(g);
nvgpu_spinunlock_irqrestore(&g->mc.intr_lock, flags);
}
}
void nvgpu_cic_mon_intr_unit_vectorid_init(struct gk20a *g, u32 unit, u32 *vectorid,
u32 num_entries)
{
unsigned long flags = 0;
u32 i = 0U;
struct nvgpu_intr_unit_info *intr_unit_info;
nvgpu_assert(num_entries <= NVGPU_CIC_INTR_VECTORID_SIZE_MAX);
nvgpu_log(g, gpu_dbg_intr, "UNIT=%d, nvecs=%d", unit, num_entries);
intr_unit_info = g->mc.intr_unit_info;
nvgpu_spinlock_irqsave(&g->mc.intr_lock, flags);
if (intr_unit_info[unit].valid == false) {
for (i = 0U; i < num_entries; i++) {
nvgpu_log(g, gpu_dbg_intr, " vec[%d] = %d", i,
*(vectorid + i));
intr_unit_info[unit].vectorid[i] = *(vectorid + i);
}
intr_unit_info[unit].vectorid_size = num_entries;
}
nvgpu_spinunlock_irqrestore(&g->mc.intr_lock, flags);
}
bool nvgpu_cic_mon_intr_is_unit_info_valid(struct gk20a *g, u32 unit)
{
struct nvgpu_intr_unit_info *intr_unit_info;
bool info_valid = false;
if (unit >= NVGPU_CIC_INTR_UNIT_MAX) {
nvgpu_err(g, "invalid unit(%d)", unit);
return false;
}
intr_unit_info = g->mc.intr_unit_info;
if (intr_unit_info[unit].valid == true) {
info_valid = true;
}
return info_valid;
}
bool nvgpu_cic_mon_intr_get_unit_info(struct gk20a *g, u32 unit, u32 *subtree,
u64 *subtree_mask)
{
if (unit >= NVGPU_CIC_INTR_UNIT_MAX) {
nvgpu_err(g, "invalid unit(%d)", unit);
return false;
}
if (nvgpu_cic_mon_intr_is_unit_info_valid(g, unit) != true) {
if (g->ops.mc.intr_get_unit_info(g, unit) != true) {
nvgpu_err(g, "failed to fetch info for unit(%d)", unit);
return false;
}
}
*subtree = g->mc.intr_unit_info[unit].subtree;
*subtree_mask = g->mc.intr_unit_info[unit].subtree_mask;
nvgpu_log(g, gpu_dbg_intr, "subtree(%d) subtree_mask(%llx)",
*subtree, *subtree_mask);
return true;
}
#endif

100
drivers/gpu/nvgpu/common/cic/mon/mon_lut.c Normal file
View File

@@ -0,0 +1,100 @@
/*
* Copyright (c) 2021, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#include <nvgpu/gk20a.h>
#include <nvgpu/log.h>
#include <nvgpu/cic_mon.h>
#include <nvgpu/nvgpu_err_info.h>
#include "cic_mon_priv.h"
int nvgpu_cic_mon_bound_check_hw_unit_id(struct gk20a *g, u32 hw_unit_id)
{
if (g->cic_mon == NULL) {
nvgpu_err(g, "CIC is not initialized");
return -EINVAL;
}
if (g->cic_mon->num_hw_modules == 0U) {
cic_dbg(g, "LUT not initialized.");
return -EINVAL;
}
if (hw_unit_id >= g->cic_mon->num_hw_modules) {
cic_dbg(g, "Invalid input HW unit ID.");
return -EINVAL;
}
return 0;
}
int nvgpu_cic_mon_bound_check_err_id(struct gk20a *g, u32 hw_unit_id,
u32 err_id)
{
int err = 0;
if ((g->cic_mon == NULL) || (g->cic_mon->err_lut == NULL)) {
cic_dbg(g, "CIC/LUT not initialized.");
return -EINVAL;
}
err = nvgpu_cic_mon_bound_check_hw_unit_id(g, hw_unit_id);
if (err != 0) {
return err;
}
if (err_id >= g->cic_mon->err_lut[hw_unit_id].num_errs) {
err = -EINVAL;
}
return err;
}
int nvgpu_cic_mon_get_err_desc(struct gk20a *g, u32 hw_unit_id,
u32 err_id, struct nvgpu_err_desc **err_desc)
{
int err = 0;
/* if (g->cic_mon != NULL) and (g->cic_mon->err_lut != NULL) check
* can be skipped here as it checked as part of
* nvgpu_cic_mon_bound_check_err_id() called below.
*/
err = nvgpu_cic_mon_bound_check_err_id(g, hw_unit_id, err_id);
if (err != 0) {
return err;
}
*err_desc = &(g->cic_mon->err_lut[hw_unit_id].errs[err_id]);
return err;
}
int nvgpu_cic_mon_get_num_hw_modules(struct gk20a *g)
{
if (g->cic_mon == NULL) {
nvgpu_err(g, "CIC is not initialized");
return -EINVAL;
}
return g->cic_mon->num_hw_modules;
}

12
drivers/gpu/nvgpu/common/cic/mmu_cic.c → drivers/gpu/nvgpu/common/cic/mon/mon_mmu.c
View File

@@ -24,9 +24,9 @@
#include <nvgpu/nvgpu_init.h>
#include <nvgpu/nvgpu_err.h>
#include <nvgpu/nvgpu_err_info.h>
#include <nvgpu/cic.h>
#include <nvgpu/cic_mon.h>
#include "cic_priv.h"
#include "cic_mon_priv.h"
void nvgpu_report_mmu_err(struct gk20a *g, u32 hw_unit, u32 err_id,
struct mmu_fault_info *fault_info, u32 status, u32 sub_err_type)
@@ -35,7 +35,7 @@ void nvgpu_report_mmu_err(struct gk20a *g, u32 hw_unit, u32 err_id,
struct nvgpu_err_desc *err_desc = NULL;
struct nvgpu_err_msg err_pkt;
if (g->ops.cic.report_err == NULL) {
if (g->ops.cic_mon.report_err == NULL) {
cic_dbg(g, "CIC does not support reporting error "
"to safety services");
return;
@@ -47,7 +47,7 @@ void nvgpu_report_mmu_err(struct gk20a *g, u32 hw_unit, u32 err_id,
goto handle_report_failure;
}
err = nvgpu_cic_get_err_desc(g, hw_unit, err_id, &err_desc);
err = nvgpu_cic_mon_get_err_desc(g, hw_unit, err_id, &err_desc);
if (err != 0) {
nvgpu_err(g, "Failed to get err_desc for "
"err_id (%u) for hw module (%u)",
@@ -104,8 +104,8 @@ void nvgpu_report_mmu_err(struct gk20a *g, u32 hw_unit, u32 err_id,
err_pkt.err_size = nvgpu_safe_cast_u64_to_u8(
sizeof(err_pkt.err_info.mmu_info));
if (g->ops.cic.report_err != NULL) {
err = g->ops.cic.report_err(g, (void *)&err_pkt,
if (g->ops.cic_mon.report_err != NULL) {
err = g->ops.cic_mon.report_err(g, (void *)&err_pkt,
sizeof(err_pkt), err_desc->is_critical);
if (err != 0) {
nvgpu_err(g, "Failed to report MMU fault: hw_unit=%u, "

2
drivers/gpu/nvgpu/common/cic/msg_cic.c → drivers/gpu/nvgpu/common/cic/mon/mon_msg.c
View File

@@ -23,7 +23,7 @@
#include <nvgpu/nvgpu_err_info.h>
#include <nvgpu/string.h>
#include "cic_priv.h"
#include "cic_mon_priv.h"
void nvgpu_init_err_msg_header(struct gpu_err_header *header)
{

12
drivers/gpu/nvgpu/common/cic/pmu_cic.c → drivers/gpu/nvgpu/common/cic/mon/mon_pmu.c
View File

@@ -24,9 +24,9 @@
#include <nvgpu/nvgpu_init.h>
#include <nvgpu/nvgpu_err.h>
#include <nvgpu/nvgpu_err_info.h>
#include <nvgpu/cic.h>
#include <nvgpu/cic_mon.h>
#include "cic_priv.h"
#include "cic_mon_priv.h"
void nvgpu_report_pmu_err(struct gk20a *g, u32 hw_unit, u32 err_id,
u32 sub_err_type, u32 status)
@@ -35,7 +35,7 @@ void nvgpu_report_pmu_err(struct gk20a *g, u32 hw_unit, u32 err_id,
struct nvgpu_err_desc *err_desc = NULL;
struct nvgpu_err_msg err_pkt;
if (g->ops.cic.report_err == NULL) {
if (g->ops.cic_mon.report_err == NULL) {
cic_dbg(g, "CIC does not support reporting error "
"to safety services");
return;
@@ -47,7 +47,7 @@ void nvgpu_report_pmu_err(struct gk20a *g, u32 hw_unit, u32 err_id,
goto handle_report_failure;
}
err = nvgpu_cic_get_err_desc(g, hw_unit, err_id, &err_desc);
err = nvgpu_cic_mon_get_err_desc(g, hw_unit, err_id, &err_desc);
if (err != 0) {
nvgpu_err(g, "Failed to get err_desc for "
"err_id (%u) for hw module (%u)",
@@ -65,8 +65,8 @@ void nvgpu_report_pmu_err(struct gk20a *g, u32 hw_unit, u32 err_id,
err_pkt.err_size = nvgpu_safe_cast_u64_to_u8(
sizeof(err_pkt.err_info.pmu_err_info));
if (g->ops.cic.report_err != NULL) {
err = g->ops.cic.report_err(g, (void *)&err_pkt,
if (g->ops.cic_mon.report_err != NULL) {
err = g->ops.cic_mon.report_err(g, (void *)&err_pkt,
sizeof(err_pkt), err_desc->is_critical);
if (err != 0) {
nvgpu_err(g, "Failed to report PMU error: "

12
drivers/gpu/nvgpu/common/cic/pri_cic.c → drivers/gpu/nvgpu/common/cic/mon/mon_pri.c
View File

@@ -24,9 +24,9 @@
#include <nvgpu/nvgpu_init.h>
#include <nvgpu/nvgpu_err.h>
#include <nvgpu/nvgpu_err_info.h>
#include <nvgpu/cic.h>
#include <nvgpu/cic_mon.h>
#include "cic_priv.h"
#include "cic_mon_priv.h"
void nvgpu_report_pri_err(struct gk20a *g, u32 hw_unit, u32 inst,
u32 err_id, u32 err_addr, u32 err_code)
@@ -35,7 +35,7 @@ void nvgpu_report_pri_err(struct gk20a *g, u32 hw_unit, u32 inst,
struct nvgpu_err_desc *err_desc = NULL;
struct nvgpu_err_msg err_pkt;
if (g->ops.cic.report_err == NULL) {
if (g->ops.cic_mon.report_err == NULL) {
cic_dbg(g, "CIC does not support reporting error "
"to safety services");
return;
@@ -47,7 +47,7 @@ void nvgpu_report_pri_err(struct gk20a *g, u32 hw_unit, u32 inst,
goto handle_report_failure;
}
err = nvgpu_cic_get_err_desc(g, hw_unit, err_id, &err_desc);
err = nvgpu_cic_mon_get_err_desc(g, hw_unit, err_id, &err_desc);
if (err != 0) {
nvgpu_err(g, "Failed to get err_desc for "
"err_id (%u) for hw module (%u)",
@@ -69,8 +69,8 @@ void nvgpu_report_pri_err(struct gk20a *g, u32 hw_unit, u32 inst,
err_pkt.err_size = nvgpu_safe_cast_u64_to_u8(
sizeof(err_pkt.err_info.pri_info));
if (g->ops.cic.report_err != NULL) {
err = g->ops.cic.report_err(g, (void *)&err_pkt,
if (g->ops.cic_mon.report_err != NULL) {
err = g->ops.cic_mon.report_err(g, (void *)&err_pkt,
sizeof(err_pkt), err_desc->is_critical);
if (err != 0) {
nvgpu_err(g, "Failed to report PRI error: "

65
drivers/gpu/nvgpu/common/cic/rm/rm_intr.c Normal file
View File

@@ -0,0 +1,65 @@
/*
* Copyright (c) 2021, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#include <nvgpu/cic_rm.h>
#include <nvgpu/gk20a.h>
#include <nvgpu/mc.h>
int nvgpu_cic_rm_wait_for_stall_interrupts(struct gk20a *g, u32 timeout)
{
/* wait until all stalling irqs are handled */
return NVGPU_COND_WAIT(&g->mc.sw_irq_stall_last_handled_cond,
nvgpu_atomic_read(&g->mc.sw_irq_stall_pending) == 0,
timeout);
}
int nvgpu_cic_rm_wait_for_nonstall_interrupts(struct gk20a *g, u32 timeout)
{
/* wait until all non-stalling irqs are handled */
return NVGPU_COND_WAIT(&g->mc.sw_irq_nonstall_last_handled_cond,
nvgpu_atomic_read(&g->mc.sw_irq_nonstall_pending) == 0,
timeout);
}
void nvgpu_cic_rm_wait_for_deferred_interrupts(struct gk20a *g)
{
int ret;
ret = nvgpu_cic_rm_wait_for_stall_interrupts(g, 0U);
if (ret != 0) {
nvgpu_err(g, "wait for stall interrupts failed %d", ret);
}
ret = nvgpu_cic_rm_wait_for_nonstall_interrupts(g, 0U);
if (ret != 0) {
nvgpu_err(g, "wait for nonstall interrupts failed %d", ret);
}
}
#ifdef CONFIG_NVGPU_NON_FUSA
void nvgpu_cic_rm_log_pending_intrs(struct gk20a *g)
{
if (g->ops.mc.log_pending_intrs != NULL) {
g->ops.mc.log_pending_intrs(g);
}
}
#endif

6
drivers/gpu/nvgpu/common/fifo/channel.c
View File

@@ -45,7 +45,7 @@
#include <nvgpu/ptimer.h>
#include <nvgpu/gk20a.h>
#include <nvgpu/mc.h>
#include <nvgpu/cic.h>
#include <nvgpu/cic_rm.h>
#include <nvgpu/nvgpu_init.h>
#include <nvgpu/engines.h>
#include <nvgpu/channel.h>
@@ -961,7 +961,7 @@ static void channel_free(struct nvgpu_channel *ch, bool force)
/* wait until all pending interrupts for recently completed
* jobs are handled */
nvgpu_cic_wait_for_deferred_interrupts(g);
nvgpu_cic_rm_wait_for_deferred_interrupts(g);
/* prevent new refs */
nvgpu_spinlock_acquire(&ch->ref_obtain_lock);
@@ -1018,7 +1018,7 @@ static void channel_free(struct nvgpu_channel *ch, bool force)
/* make sure we don't have deferred interrupts pending that
* could still touch the channel */
nvgpu_cic_wait_for_deferred_interrupts(g);
nvgpu_cic_rm_wait_for_deferred_interrupts(g);
unbind:
g->ops.channel.unbind(ch);

6
drivers/gpu/nvgpu/common/fifo/fifo.c
View File

@@ -34,7 +34,7 @@
#include <nvgpu/tsg.h>
#include <nvgpu/vm_area.h>
#include <nvgpu/nvgpu_err.h>
#include <nvgpu/cic.h>
#include <nvgpu/cic_mon.h>
#include <nvgpu/mc.h>
#include <nvgpu/swprofile.h>
#include <nvgpu/fifo/swprofile.h>
@@ -281,9 +281,9 @@ static void disable_fifo_interrupts(struct gk20a *g)
g->ops.fifo.intr_1_enable(g, false);
if (g->ops.fifo.intr_top_enable == NULL) {
nvgpu_cic_intr_stall_unit_config(g, NVGPU_CIC_INTR_UNIT_FIFO,
nvgpu_cic_mon_intr_stall_unit_config(g, NVGPU_CIC_INTR_UNIT_FIFO,
NVGPU_CIC_INTR_DISABLE);
nvgpu_cic_intr_nonstall_unit_config(g, NVGPU_CIC_INTR_UNIT_FIFO,
nvgpu_cic_mon_intr_nonstall_unit_config(g, NVGPU_CIC_INTR_UNIT_FIFO,
NVGPU_CIC_INTR_DISABLE);
} else {
g->ops.fifo.intr_top_enable(g, NVGPU_CIC_INTR_DISABLE);

4
drivers/gpu/nvgpu/common/fifo/preempt.c
View File

@@ -29,7 +29,7 @@
#include <nvgpu/tsg.h>
#include <nvgpu/preempt.h>
#include <nvgpu/nvgpu_err.h>
#include <nvgpu/cic.h>
#include <nvgpu/cic_rm.h>
#include <nvgpu/rc.h>
#ifdef CONFIG_NVGPU_LS_PMU
#include <nvgpu/pmu/mutex.h>
@@ -103,7 +103,7 @@ int nvgpu_fifo_preempt_tsg(struct gk20a *g, struct nvgpu_tsg *tsg)
break;
}
ret = nvgpu_cic_wait_for_stall_interrupts(g, preempt_retry_timeout);
ret = nvgpu_cic_rm_wait_for_stall_interrupts(g, preempt_retry_timeout);
if (ret != 0) {
nvgpu_log_info(g, "wait for stall interrupts failed %d", ret);
}

14
drivers/gpu/nvgpu/common/gr/gr.c
View File

@@ -45,7 +45,7 @@
#include <nvgpu/power_features/cg.h>
#include <nvgpu/power_features/pg.h>
#include <nvgpu/mc.h>
#include <nvgpu/cic.h>
#include <nvgpu/cic_mon.h>
#include <nvgpu/device.h>
#include <nvgpu/engines.h>
#include <nvgpu/grmgr.h>
@@ -187,9 +187,9 @@ static void disable_gr_interrupts(struct gk20a *g)
g->ops.gr.intr.enable_exceptions(g, g->gr->config, false);
/** Disable interrupts at MC level */
nvgpu_cic_intr_stall_unit_config(g, NVGPU_CIC_INTR_UNIT_GR,
nvgpu_cic_mon_intr_stall_unit_config(g, NVGPU_CIC_INTR_UNIT_GR,
NVGPU_CIC_INTR_DISABLE);
nvgpu_cic_intr_nonstall_unit_config(g, NVGPU_CIC_INTR_UNIT_GR,
nvgpu_cic_mon_intr_nonstall_unit_config(g, NVGPU_CIC_INTR_UNIT_GR,
NVGPU_CIC_INTR_DISABLE);
}
@@ -591,8 +591,8 @@ static int gr_init_prepare_hw(struct gk20a *g)
nvgpu_log(g, gpu_dbg_fn | gpu_dbg_gr, " ");
/** Enable interrupts at MC level */
nvgpu_cic_intr_stall_unit_config(g, NVGPU_CIC_INTR_UNIT_GR, NVGPU_CIC_INTR_ENABLE);
nvgpu_cic_intr_nonstall_unit_config(g, NVGPU_CIC_INTR_UNIT_GR, NVGPU_CIC_INTR_ENABLE);
nvgpu_cic_mon_intr_stall_unit_config(g, NVGPU_CIC_INTR_UNIT_GR, NVGPU_CIC_INTR_ENABLE);
nvgpu_cic_mon_intr_nonstall_unit_config(g, NVGPU_CIC_INTR_UNIT_GR, NVGPU_CIC_INTR_ENABLE);
return nvgpu_gr_exec_with_ret_for_each_instance(g,
gr_init_prepare_hw_impl(g));
@@ -709,8 +709,8 @@ static int nvgpu_gr_enable_hw_for_instance(struct gk20a *g)
nvgpu_cg_elcg_disable_no_wait(g);
/** Enable interrupts at MC level */
nvgpu_cic_intr_stall_unit_config(g, NVGPU_CIC_INTR_UNIT_GR, NVGPU_CIC_INTR_ENABLE);
nvgpu_cic_intr_nonstall_unit_config(g, NVGPU_CIC_INTR_UNIT_GR, NVGPU_CIC_INTR_ENABLE);
nvgpu_cic_mon_intr_stall_unit_config(g, NVGPU_CIC_INTR_UNIT_GR, NVGPU_CIC_INTR_ENABLE);
nvgpu_cic_mon_intr_nonstall_unit_config(g, NVGPU_CIC_INTR_UNIT_GR, NVGPU_CIC_INTR_ENABLE);
err = gr_init_prepare_hw_impl(g);
if (err != 0) {

31
drivers/gpu/nvgpu/common/init/nvgpu_init.c
View File

@@ -46,7 +46,8 @@
#ifdef CONFIG_NVGPU_NON_FUSA
#include <nvgpu/ptimer.h>
#endif
#include <nvgpu/cic.h>
#include <nvgpu/cic_mon.h>
#include <nvgpu/cic_rm.h>
#ifdef CONFIG_NVGPU_LS_PMU
#include <nvgpu/pmu/pmu_pstate.h>
@@ -73,9 +74,9 @@ void nvgpu_check_gpu_state(struct gk20a *g)
static void gk20a_mask_interrupts(struct gk20a *g)
{
nvgpu_cic_intr_mask(g);
nvgpu_cic_mon_intr_mask(g);
#ifdef CONFIG_NVGPU_NON_FUSA
nvgpu_cic_log_pending_intrs(g);
nvgpu_cic_rm_log_pending_intrs(g);
#endif
}
@@ -362,7 +363,15 @@ int nvgpu_prepare_poweroff(struct gk20a *g)
* This will ensure that CIC will not get probed
* after it's deinit.
*/
nvgpu_cic_deinit_common(g);
ret = nvgpu_cic_mon_deinit(g);
if (ret != 0) {
nvgpu_err(g, "Failed to deinit CIC-mon.");
}
ret = nvgpu_cic_mon_remove(g);
if (ret != 0) {
nvgpu_err(g, "Failed to remove CIC-mon.");
}
return ret;
}
@@ -568,14 +577,14 @@ static int nvgpu_init_interrupt_setup(struct gk20a *g)
/**
* Disable all interrupts at the start.
*/
nvgpu_cic_intr_mask(g);
nvgpu_cic_mon_intr_mask(g);
#ifdef CONFIG_NVGPU_NON_FUSA
/**
* For certain chips like gm20b, there is global interrupt control in
* registers mc_intr_en_*_r. Program them here upfront.
*/
nvgpu_cic_intr_enable(g);
nvgpu_cic_mon_intr_enable(g);
#endif
return 0;
@@ -727,9 +736,15 @@ int nvgpu_early_poweron(struct gk20a *g)
/* Initialize CIC early on before the interrupts are
* enabled.
*/
err = nvgpu_cic_init_common(g);
err = nvgpu_cic_mon_setup(g);
if (err != 0) {
nvgpu_err(g, "CIC Initialization failed[%d]", err);
nvgpu_err(g, "CIC-mon setup failed[%d]", err);
goto done;
}
err = nvgpu_cic_mon_init_lut(g);
if (err != 0) {
nvgpu_err(g, "CIC LUT Initialization failed[%d]", err);
goto done;
}
done:

4
drivers/gpu/nvgpu/common/ltc/ltc.c
View File

@@ -24,7 +24,7 @@
#include <nvgpu/dma.h>
#include <nvgpu/nvgpu_mem.h>
#include <nvgpu/gk20a.h>
#include <nvgpu/cic.h>
#include <nvgpu/cic_mon.h>
#include <nvgpu/string.h>
void nvgpu_ltc_remove_support(struct gk20a *g)
@@ -74,7 +74,7 @@ int nvgpu_init_ltc_support(struct gk20a *g)
}
if (g->ops.ltc.intr.configure != NULL) {
nvgpu_cic_intr_stall_unit_config(g, NVGPU_CIC_INTR_UNIT_LTC,
nvgpu_cic_mon_intr_stall_unit_config(g, NVGPU_CIC_INTR_UNIT_LTC,
NVGPU_CIC_INTR_ENABLE);
g->ops.ltc.intr.configure(g);
}

4
drivers/gpu/nvgpu/common/nvlink/nvlink.c
View File

@@ -27,7 +27,7 @@
#include <nvgpu/device.h>
#include <nvgpu/nvlink_bios.h>
#include <nvgpu/device.h>
#include <nvgpu/cic.h>
#include <nvgpu/cic_mon.h>
#include <nvgpu/errata.h>
#ifdef CONFIG_NVGPU_NVLINK
@@ -236,7 +236,7 @@ int nvgpu_nvlink_early_init(struct gk20a *g)
nvgpu_err(g, "Failed to reset NVLINK unit");
}
nvgpu_cic_intr_stall_unit_config(g, NVGPU_CIC_INTR_UNIT_NVLINK,
nvgpu_cic_mon_intr_stall_unit_config(g, NVGPU_CIC_INTR_UNIT_NVLINK,
NVGPU_CIC_INTR_ENABLE);
err = g->ops.nvlink.discover_link(g);

5
drivers/gpu/nvgpu/hal/bus/bus_ga10b.c
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2020-2021, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -25,6 +25,7 @@
#include <nvgpu/soc.h>
#include <nvgpu/bug.h>
#include <nvgpu/gk20a.h>
#include <nvgpu/cic_mon.h>
#include <nvgpu/nvgpu_err.h>
#include "bus_ga10b.h"
@@ -76,7 +77,7 @@ int ga10b_bus_init_hw(struct gk20a *g)
nvgpu_log_info(g, "bus fb_timeout=0x%x",
bus_fb_timeout_period_v(nvgpu_readl(g, bus_fb_timeout_r())));
nvgpu_cic_intr_stall_unit_config(g, NVGPU_CIC_INTR_UNIT_BUS, NVGPU_CIC_INTR_ENABLE);
nvgpu_cic_mon_intr_stall_unit_config(g, NVGPU_CIC_INTR_UNIT_BUS, NVGPU_CIC_INTR_ENABLE);
nvgpu_writel(g, bus_intr_en_0_r(), intr_en_mask);
return 0;

4
drivers/gpu/nvgpu/hal/bus/bus_gk20a_fusa.c
View File

@@ -28,7 +28,7 @@
#include <nvgpu/gk20a.h>
#include <nvgpu/nvgpu_sgt.h>
#include <nvgpu/nvgpu_err.h>
#include <nvgpu/cic.h>
#include <nvgpu/cic_mon.h>
#include <nvgpu/mc.h>
#include "bus_gk20a.h"
@@ -39,7 +39,7 @@ int gk20a_bus_init_hw(struct gk20a *g)
{
u32 intr_en_mask = 0U;
nvgpu_cic_intr_nonstall_unit_config(g, NVGPU_CIC_INTR_UNIT_BUS, NVGPU_CIC_INTR_ENABLE);
nvgpu_cic_mon_intr_nonstall_unit_config(g, NVGPU_CIC_INTR_UNIT_BUS, NVGPU_CIC_INTR_ENABLE);
/*
* Note: bus_intr_en_0 is for routing intr to stall tree (mc_intr_0)

4
drivers/gpu/nvgpu/hal/bus/bus_tu104.c
View File

@@ -24,7 +24,7 @@
#include <nvgpu/soc.h>
#include <nvgpu/io.h>
#include <nvgpu/mm.h>
#include <nvgpu/cic.h>
#include <nvgpu/cic_mon.h>
#include <nvgpu/gk20a.h>
#include "bus_tu104.h"
@@ -36,7 +36,7 @@ int tu104_bus_init_hw(struct gk20a *g)
{
u32 intr_en_mask = 0U;
nvgpu_cic_intr_stall_unit_config(g, NVGPU_CIC_INTR_UNIT_BUS, NVGPU_CIC_INTR_ENABLE);
nvgpu_cic_mon_intr_stall_unit_config(g, NVGPU_CIC_INTR_UNIT_BUS, NVGPU_CIC_INTR_ENABLE);
/*
* Note: bus_intr_en_0 is for routing intr to stall tree (mc_intr_0)

2
drivers/gpu/nvgpu/hal/ce/ce2_gk20a.c
View File

@@ -29,7 +29,7 @@
#include <nvgpu/io.h>
#include <nvgpu/utils.h>
#include <nvgpu/gk20a.h>
#include <nvgpu/cic.h>
#include <nvgpu/cic_mon.h>
#include <nvgpu/mc.h>
#include <nvgpu/channel.h>
#include <nvgpu/engines.h>

5
drivers/gpu/nvgpu/hal/ce/ce_ga10b_fusa.c
View File

@@ -1,7 +1,7 @@
/*
* Ampere GPU series Copy Engine.
*
* Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2020-2021, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -27,6 +27,7 @@
#include <nvgpu/device.h>
#include <nvgpu/gk20a.h>
#include <nvgpu/fifo.h>
#include <nvgpu/cic_mon.h>
#include <nvgpu/mc.h>
#include "hal/ce/ce_gv11b.h"
@@ -159,7 +160,7 @@ void ga10b_ce_init_hw(struct gk20a *g)
/*
* Initalize struct nvgpu_mc with POR values of non-stall vectors ids.
*/
nvgpu_cic_intr_unit_vectorid_init(g, NVGPU_CIC_INTR_UNIT_CE,
nvgpu_cic_mon_intr_unit_vectorid_init(g, NVGPU_CIC_INTR_UNIT_CE,
nonstall_vectorid_tree, num_nonstall_vectors);
}

2
drivers/gpu/nvgpu/hal/ce/ce_gp10b_fusa.c
View File

@@ -25,7 +25,7 @@
#include <nvgpu/io.h>
#include <nvgpu/gk20a.h>
#include <nvgpu/mc.h>
#include <nvgpu/cic.h>
#include <nvgpu/cic_mon.h>
#include <nvgpu/nvgpu_err.h>
#include "ce_gp10b.h"

4
drivers/gpu/nvgpu/hal/cic/cic_gv11b.h → drivers/gpu/nvgpu/hal/cic/mon/cic_gv11b.h
View File

@@ -26,11 +26,11 @@
#include <nvgpu/nvgpu_err_info.h>
struct gk20a;
struct nvgpu_cic;
struct nvgpu_cic_mon;
extern struct nvgpu_err_hw_module gv11b_err_lut[];
extern u32 size_of_gv11b_lut;
int gv11b_cic_init(struct gk20a *g, struct nvgpu_cic *cic);
int gv11b_cic_mon_init(struct gk20a *g, struct nvgpu_cic_mon *cic_mon);
#endif /* CIC_GV11B_H */

10
drivers/gpu/nvgpu/hal/cic/cic_gv11b_fusa.c → drivers/gpu/nvgpu/hal/cic/mon/init_gv11b_fusa.c
View File

@@ -22,17 +22,17 @@
#include <nvgpu/log.h>
#include "common/cic/cic_priv.h"
#include "common/cic/mon/cic_mon_priv.h"
#include "cic_gv11b.h"
int gv11b_cic_init(struct gk20a *g, struct nvgpu_cic *cic)
int gv11b_cic_mon_init(struct gk20a *g, struct nvgpu_cic_mon *cic_mon)
{
if (cic == NULL) {
if (cic_mon == NULL) {
nvgpu_err(g, "Invalid CIC reference pointer.");
return -EINVAL;
}
cic->err_lut = gv11b_err_lut;
cic->num_hw_modules = size_of_gv11b_lut;
cic_mon->err_lut = gv11b_err_lut;
cic_mon->num_hw_modules = size_of_gv11b_lut;
return 0;
}

2
drivers/gpu/nvgpu/hal/cic/cic_lut_gv11b_fusa.c → drivers/gpu/nvgpu/hal/cic/mon/lut_gv11b_fusa.c
View File

@@ -23,7 +23,7 @@
#include <nvgpu/nvgpu_err.h>
#include <nvgpu/nvgpu_err_info.h>
#include <nvgpu/static_analysis.h>
#include "common/cic/cic_priv.h"
#include "common/cic/mon/cic_mon_priv.h"
#include "cic_gv11b.h"
/*

1
drivers/gpu/nvgpu/hal/fb/fb_mmu_fault_ga10b_fusa.c
View File

@@ -27,7 +27,6 @@
#include <nvgpu/utils.h>
#include <nvgpu/gk20a.h>
#include <nvgpu/mmu_fault.h>
#include <nvgpu/cic.h>
#include "hal/fb/fb_mmu_fault_gv11b.h"
#include "hal/mm/mmu_fault/mmu_fault_gv11b.h"

38
drivers/gpu/nvgpu/hal/fb/intr/fb_intr_ga10b_fusa.c
View File

@@ -26,7 +26,7 @@
#include <nvgpu/io.h>
#include <nvgpu/gk20a.h>
#include <nvgpu/mc.h>
#include <nvgpu/cic.h>
#include <nvgpu/cic_mon.h>
#include "hal/fb/intr/fb_intr_ecc_gv11b.h"
#include "hal/fb/fb_mmu_fault_ga10b.h"
@@ -44,33 +44,33 @@ void ga10b_fb_intr_vectorid_init(struct gk20a *g)
ecc_error = nvgpu_readl(g, fb_mmu_int_vector_ecc_error_r());
vectorid = fb_mmu_int_vector_ecc_error_vector_v(ecc_error);
nvgpu_cic_intr_unit_vectorid_init(g, NVGPU_CIC_INTR_UNIT_MMU_FAULT_ECC_ERROR,
nvgpu_cic_mon_intr_unit_vectorid_init(g, NVGPU_CIC_INTR_UNIT_MMU_FAULT_ECC_ERROR,
&vectorid, NVGPU_CIC_INTR_VECTORID_SIZE_ONE);
info_fault = nvgpu_readl(g, fb_mmu_int_vector_info_fault_r());
vectorid = fb_mmu_int_vector_info_fault_vector_v(info_fault);
nvgpu_cic_intr_unit_vectorid_init(g, NVGPU_CIC_INTR_UNIT_MMU_INFO_FAULT,
nvgpu_cic_mon_intr_unit_vectorid_init(g, NVGPU_CIC_INTR_UNIT_MMU_INFO_FAULT,
&vectorid, NVGPU_CIC_INTR_VECTORID_SIZE_ONE);
nonreplay_fault = nvgpu_readl(g, fb_mmu_int_vector_fault_r(
NVGPU_MMU_FAULT_NONREPLAY_REG_INDX));
vectorid = fb_mmu_int_vector_fault_notify_v(nonreplay_fault);
nvgpu_cic_intr_unit_vectorid_init(g, NVGPU_CIC_INTR_UNIT_MMU_NON_REPLAYABLE_FAULT,
nvgpu_cic_mon_intr_unit_vectorid_init(g, NVGPU_CIC_INTR_UNIT_MMU_NON_REPLAYABLE_FAULT,
&vectorid, NVGPU_CIC_INTR_VECTORID_SIZE_ONE);
vectorid = fb_mmu_int_vector_fault_error_v(nonreplay_fault);
nvgpu_cic_intr_unit_vectorid_init(g, NVGPU_CIC_INTR_UNIT_MMU_NON_REPLAYABLE_FAULT_ERROR,
nvgpu_cic_mon_intr_unit_vectorid_init(g, NVGPU_CIC_INTR_UNIT_MMU_NON_REPLAYABLE_FAULT_ERROR,
&vectorid, NVGPU_CIC_INTR_VECTORID_SIZE_ONE);
#ifdef CONFIG_NVGPU_REPLAYABLE_FAULT
replay_fault = nvgpu_readl(g, fb_mmu_int_vector_fault_r(
NVGPU_MMU_FAULT_REPLAY_REG_INDX));
vectorid = fb_mmu_int_vector_fault_notify_v(replay_fault);
nvgpu_cic_intr_unit_vectorid_init(g, NVGPU_CIC_INTR_UNIT_MMU_REPLAYABLE_FAULT,
nvgpu_cic_mon_intr_unit_vectorid_init(g, NVGPU_CIC_INTR_UNIT_MMU_REPLAYABLE_FAULT,
&vectorid, NVGPU_CIC_INTR_VECTORID_SIZE_ONE);
vectorid = fb_mmu_int_vector_fault_error_v(replay_fault);
nvgpu_cic_intr_unit_vectorid_init(g, NVGPU_CIC_INTR_UNIT_MMU_REPLAYABLE_FAULT_ERROR,
nvgpu_cic_mon_intr_unit_vectorid_init(g, NVGPU_CIC_INTR_UNIT_MMU_REPLAYABLE_FAULT_ERROR,
&vectorid, NVGPU_CIC_INTR_VECTORID_SIZE_ONE);
#endif
@@ -79,18 +79,18 @@ void ga10b_fb_intr_vectorid_init(struct gk20a *g)
void ga10b_fb_intr_enable(struct gk20a *g)
{
nvgpu_cic_intr_stall_unit_config(g,
nvgpu_cic_mon_intr_stall_unit_config(g,
NVGPU_CIC_INTR_UNIT_MMU_FAULT_ECC_ERROR, NVGPU_CIC_INTR_ENABLE);
nvgpu_cic_intr_stall_unit_config(g,
nvgpu_cic_mon_intr_stall_unit_config(g,
NVGPU_CIC_INTR_UNIT_MMU_INFO_FAULT, NVGPU_CIC_INTR_ENABLE);
nvgpu_cic_intr_stall_unit_config(g,
nvgpu_cic_mon_intr_stall_unit_config(g,
NVGPU_CIC_INTR_UNIT_MMU_NON_REPLAYABLE_FAULT, NVGPU_CIC_INTR_ENABLE);
nvgpu_cic_intr_stall_unit_config(g,
nvgpu_cic_mon_intr_stall_unit_config(g,
NVGPU_CIC_INTR_UNIT_MMU_NON_REPLAYABLE_FAULT_ERROR, NVGPU_CIC_INTR_ENABLE);
#ifdef CONFIG_NVGPU_REPLAYABLE_FAULT
nvgpu_cic_intr_stall_unit_config(g,
nvgpu_cic_mon_intr_stall_unit_config(g,
NVGPU_CIC_INTR_UNIT_MMU_REPLAYABLE_FAULT, NVGPU_CIC_INTR_ENABLE);
nvgpu_cic_intr_stall_unit_config(g,
nvgpu_cic_mon_intr_stall_unit_config(g,
NVGPU_CIC_INTR_UNIT_MMU_REPLAYABLE_FAULT_ERROR, NVGPU_CIC_INTR_ENABLE);
#endif
/* TBD hub_access_cntr_intr */
@@ -98,18 +98,18 @@ void ga10b_fb_intr_enable(struct gk20a *g)
void ga10b_fb_intr_disable(struct gk20a *g)
{
nvgpu_cic_intr_stall_unit_config(g,
nvgpu_cic_mon_intr_stall_unit_config(g,
NVGPU_CIC_INTR_UNIT_MMU_FAULT_ECC_ERROR, NVGPU_CIC_INTR_DISABLE);
nvgpu_cic_intr_stall_unit_config(g,
nvgpu_cic_mon_intr_stall_unit_config(g,
NVGPU_CIC_INTR_UNIT_MMU_INFO_FAULT, NVGPU_CIC_INTR_DISABLE);
nvgpu_cic_intr_stall_unit_config(g,
nvgpu_cic_mon_intr_stall_unit_config(g,
NVGPU_CIC_INTR_UNIT_MMU_NON_REPLAYABLE_FAULT, NVGPU_CIC_INTR_DISABLE);
nvgpu_cic_intr_stall_unit_config(g,
nvgpu_cic_mon_intr_stall_unit_config(g,
NVGPU_CIC_INTR_UNIT_MMU_NON_REPLAYABLE_FAULT_ERROR, NVGPU_CIC_INTR_DISABLE);
#ifdef CONFIG_NVGPU_REPLAYABLE_FAULT
nvgpu_cic_intr_stall_unit_config(g,
nvgpu_cic_mon_intr_stall_unit_config(g,
NVGPU_CIC_INTR_UNIT_MMU_REPLAYABLE_FAULT, NVGPU_CIC_INTR_DISABLE);
nvgpu_cic_intr_stall_unit_config(g,
nvgpu_cic_mon_intr_stall_unit_config(g,
NVGPU_CIC_INTR_UNIT_MMU_REPLAYABLE_FAULT_ERROR, NVGPU_CIC_INTR_DISABLE);
#endif
/* TBD hub_access_cntr_intr */

6
drivers/gpu/nvgpu/hal/fb/intr/fb_intr_gv11b_fusa.c
View File

@@ -25,7 +25,7 @@
#include <nvgpu/log.h>
#include <nvgpu/io.h>
#include <nvgpu/gk20a.h>
#include <nvgpu/cic.h>
#include <nvgpu/cic_mon.h>
#include <nvgpu/mc.h>
#include "hal/fb/fb_gv11b.h"
@@ -48,7 +48,7 @@ void gv11b_fb_intr_enable(struct gk20a *g)
#endif
fb_niso_intr_en_set_mmu_ecc_uncorrected_error_notify_m();
nvgpu_cic_intr_stall_unit_config(g, NVGPU_CIC_INTR_UNIT_HUB, NVGPU_CIC_INTR_ENABLE);
nvgpu_cic_mon_intr_stall_unit_config(g, NVGPU_CIC_INTR_UNIT_HUB, NVGPU_CIC_INTR_ENABLE);
nvgpu_writel(g, fb_niso_intr_en_set_r(0), mask);
}
@@ -68,7 +68,7 @@ void gv11b_fb_intr_disable(struct gk20a *g)
nvgpu_writel(g, fb_niso_intr_en_clr_r(0), mask);
nvgpu_cic_intr_stall_unit_config(g, NVGPU_CIC_INTR_UNIT_HUB, NVGPU_CIC_INTR_DISABLE);
nvgpu_cic_mon_intr_stall_unit_config(g, NVGPU_CIC_INTR_UNIT_HUB, NVGPU_CIC_INTR_DISABLE);
}
void gv11b_fb_intr_isr(struct gk20a *g, u32 intr_unit_bitmask)

4
drivers/gpu/nvgpu/hal/fbpa/fbpa_tu104.c
View File

@@ -28,7 +28,7 @@
#include <nvgpu/gk20a.h>
#include <nvgpu/hw/tu104/hw_fbpa_tu104.h>
#include <nvgpu/mc.h>
#include <nvgpu/cic.h>
#include <nvgpu/cic_mon.h>
#include <nvgpu/nvgpu_init.h>
#include "hal/fbpa/fbpa_tu104.h"
@@ -41,7 +41,7 @@ int tu104_fbpa_init(struct gk20a *g)
val |= fbpa_ecc_intr_ctrl_sec_intr_en_enabled_f() |
fbpa_ecc_intr_ctrl_ded_intr_en_enabled_f();
nvgpu_cic_intr_stall_unit_config(g, NVGPU_CIC_INTR_UNIT_FBPA, NVGPU_CIC_INTR_ENABLE);
nvgpu_cic_mon_intr_stall_unit_config(g, NVGPU_CIC_INTR_UNIT_FBPA, NVGPU_CIC_INTR_ENABLE);
nvgpu_writel(g, fbpa_ecc_intr_ctrl_r(), val);
/* read back broadcast register */

6
drivers/gpu/nvgpu/hal/fifo/fifo_gk20a.c
View File

@@ -27,7 +27,7 @@
#include <nvgpu/fifo.h>
#include <nvgpu/gk20a.h>
#include <nvgpu/power_features/cg.h>
#include <nvgpu/cic.h>
#include <nvgpu/cic_mon.h>
#include <nvgpu/mc.h>
#include "hal/fifo/fifo_gk20a.h"
@@ -36,8 +36,8 @@
static void enable_fifo_interrupts(struct gk20a *g)
{
nvgpu_cic_intr_stall_unit_config(g, NVGPU_CIC_INTR_UNIT_FIFO, NVGPU_CIC_INTR_ENABLE);
nvgpu_cic_intr_nonstall_unit_config(g, NVGPU_CIC_INTR_UNIT_FIFO,
nvgpu_cic_mon_intr_stall_unit_config(g, NVGPU_CIC_INTR_UNIT_FIFO, NVGPU_CIC_INTR_ENABLE);
nvgpu_cic_mon_intr_nonstall_unit_config(g, NVGPU_CIC_INTR_UNIT_FIFO,
NVGPU_CIC_INTR_ENABLE);
g->ops.fifo.intr_0_enable(g, true);

6
drivers/gpu/nvgpu/hal/fifo/fifo_gv11b_fusa.c
View File

@@ -29,7 +29,7 @@
#include <nvgpu/gk20a.h>
#include <nvgpu/power_features/cg.h>
#include <nvgpu/static_analysis.h>
#include <nvgpu/cic.h>
#include <nvgpu/cic_mon.h>
#include <nvgpu/mc.h>
#include <nvgpu/hw/gv11b/hw_fifo_gv11b.h>
@@ -38,9 +38,9 @@
static void enable_fifo_interrupts(struct gk20a *g)
{
nvgpu_cic_intr_stall_unit_config(g, NVGPU_CIC_INTR_UNIT_FIFO,
nvgpu_cic_mon_intr_stall_unit_config(g, NVGPU_CIC_INTR_UNIT_FIFO,
NVGPU_CIC_INTR_ENABLE);
nvgpu_cic_intr_nonstall_unit_config(g, NVGPU_CIC_INTR_UNIT_FIFO,
nvgpu_cic_mon_intr_nonstall_unit_config(g, NVGPU_CIC_INTR_UNIT_FIFO,
NVGPU_CIC_INTR_ENABLE);
g->ops.fifo.intr_0_enable(g, true);

12
drivers/gpu/nvgpu/hal/fifo/fifo_intr_ga10b_fusa.c
View File

@@ -26,7 +26,7 @@
#include <nvgpu/runlist.h>
#include <nvgpu/mc.h>
#include <nvgpu/nvgpu_err.h>
#include <nvgpu/cic.h>
#include <nvgpu/cic_mon.h>
#include <nvgpu/rc.h>
#include "fifo_utils_ga10b.h"
@@ -116,7 +116,7 @@ void ga10b_fifo_runlist_intr_vectorid_init(struct gk20a *g)
intr_unit = NVGPU_CIC_INTR_UNIT_RUNLIST_TREE_0 + intr_tree;
if (nvgpu_cic_intr_is_unit_info_valid(g, intr_unit) == true) {
if (nvgpu_cic_mon_intr_is_unit_info_valid(g, intr_unit) == true) {
/* intr_unit_info is already set by s/w */
continue;
}
@@ -136,7 +136,7 @@ void ga10b_fifo_runlist_intr_vectorid_init(struct gk20a *g)
"init runlist: %u intr_tree_%d vectorid",
i, intr_tree);
}
nvgpu_cic_intr_unit_vectorid_init(g, intr_unit,
nvgpu_cic_mon_intr_unit_vectorid_init(g, intr_unit,
vectorid_tree, num_vectorid);
}
@@ -145,17 +145,17 @@ void ga10b_fifo_runlist_intr_vectorid_init(struct gk20a *g)
void ga10b_fifo_intr_top_enable(struct gk20a *g, bool enable)
{
if (enable) {
nvgpu_cic_intr_stall_unit_config(g,
nvgpu_cic_mon_intr_stall_unit_config(g,
NVGPU_CIC_INTR_UNIT_RUNLIST_TREE_0, NVGPU_CIC_INTR_ENABLE);
/**
* RUNLIST_TREE_1 interrupts are not enabled as all runlist
* interrupts are routed to runlist_tree_0
*/
nvgpu_cic_intr_stall_unit_config(g,
nvgpu_cic_mon_intr_stall_unit_config(g,
NVGPU_CIC_INTR_UNIT_RUNLIST_TREE_1, NVGPU_CIC_INTR_DISABLE);
} else {
nvgpu_cic_intr_stall_unit_config(g,
nvgpu_cic_mon_intr_stall_unit_config(g,
NVGPU_CIC_INTR_UNIT_RUNLIST_TREE_0, NVGPU_CIC_INTR_DISABLE);
}
}

2
drivers/gpu/nvgpu/hal/fifo/fifo_intr_gk20a_fusa.c
View File

@@ -30,7 +30,7 @@
#include <nvgpu/tsg.h>
#include <nvgpu/rc.h>
#include <nvgpu/nvgpu_err.h>
#include <nvgpu/cic.h>
#include <nvgpu/cic_mon.h>
#include <nvgpu/engines.h>
#include <hal/fifo/fifo_intr_gk20a.h>

2
drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gm20b_fusa.c
View File

@@ -22,7 +22,7 @@
#include <nvgpu/gk20a.h>
#include <nvgpu/mc.h>
#include <nvgpu/cic.h>
#include <nvgpu/cic_mon.h>
#include <nvgpu/io.h>
#include <nvgpu/class.h>
#include <nvgpu/static_analysis.h>

4
drivers/gpu/nvgpu/hal/init/hal_gm20b.c
View File

@@ -1060,7 +1060,7 @@ static const struct gops_grmgr gm20b_ops_grmgr = {
.init_gr_manager = nvgpu_init_gr_manager,
};
static const struct gops_cic gm20b_ops_cic = {
static const struct gops_cic_mon gm20b_ops_cic_mon = {
.init = NULL,
.report_err = NULL,
};
@@ -1170,7 +1170,7 @@ int gm20b_init_hal(struct gk20a *g)
gops->tpc = gm20b_ops_tpc;
#endif
gops->grmgr = gm20b_ops_grmgr;
gops->cic = gm20b_ops_cic;
gops->cic_mon = gm20b_ops_cic_mon;
gops->chip_init_gpu_characteristics = nvgpu_init_gpu_characteristics;
gops->get_litter_value = gm20b_get_litter_value;
gops->semaphore_wakeup = nvgpu_channel_semaphore_wakeup;

4
drivers/gpu/nvgpu/hal/init/hal_gp10b.c
View File

@@ -1159,7 +1159,7 @@ static const struct gops_grmgr gp10b_ops_grmgr = {
.init_gr_manager = nvgpu_init_gr_manager,
};
static const struct gops_cic gp10b_ops_cic = {
static const struct gops_cic_mon gp10b_ops_cic_mon = {
.init = NULL,
.report_err = NULL,
};
@@ -1259,7 +1259,7 @@ int gp10b_init_hal(struct gk20a *g)
gops->tpc = gp10b_ops_tpc;
#endif
gops->grmgr = gp10b_ops_grmgr;
gops->cic = gp10b_ops_cic;
gops->cic_mon = gp10b_ops_cic_mon;
gops->chip_init_gpu_characteristics = gp10b_init_gpu_characteristics;
gops->get_litter_value = gp10b_get_litter_value;
gops->semaphore_wakeup = nvgpu_channel_semaphore_wakeup;

12
drivers/gpu/nvgpu/hal/init/hal_gv11b.c
View File

@@ -189,7 +189,7 @@
#include "hal/fifo/channel_gm20b.h"
#include "hal/fifo/channel_gv11b.h"
#include "hal/cic/cic_gv11b.h"
#include "hal/cic/mon/cic_gv11b.h"
#ifdef CONFIG_NVGPU_TPC_POWERGATE
#include "hal/tpc/tpc_gv11b.h"
@@ -212,7 +212,7 @@
#include <nvgpu/gr/gr_intr.h>
#include <nvgpu/nvgpu_init.h>
#include <nvgpu/grmgr.h>
#include <nvgpu/cic.h>
#include <nvgpu/cic_mon.h>
#include <nvgpu/hw/gv11b/hw_pwr_gv11b.h>
@@ -1438,9 +1438,9 @@ static const struct gops_grmgr gv11b_ops_grmgr = {
.init_gr_manager = nvgpu_init_gr_manager,
};
static const struct gops_cic gv11b_ops_cic = {
.init = gv11b_cic_init,
.report_err = nvgpu_cic_report_err_safety_services,
static const struct gops_cic_mon gv11b_ops_cic_mon = {
.init = gv11b_cic_mon_init,
.report_err = nvgpu_cic_mon_report_err_safety_services,
};
int gv11b_init_hal(struct gk20a *g)
@@ -1539,7 +1539,7 @@ int gv11b_init_hal(struct gk20a *g)
gops->tpc = gv11b_ops_tpc;
#endif
gops->grmgr = gv11b_ops_grmgr;
gops->cic = gv11b_ops_cic;
gops->cic_mon = gv11b_ops_cic_mon;
gops->chip_init_gpu_characteristics = gv11b_init_gpu_characteristics;
gops->get_litter_value = gv11b_get_litter_value;
gops->semaphore_wakeup = nvgpu_channel_semaphore_wakeup;

4
drivers/gpu/nvgpu/hal/init/hal_tu104.c
View File

@@ -1626,7 +1626,7 @@ static const struct gops_grmgr tu104_ops_grmgr = {
};
#endif
static const struct gops_cic tu104_ops_cic = {
static const struct gops_cic_mon tu104_ops_cic_mon = {
.init = NULL,
.report_err = NULL,
};
@@ -1740,7 +1740,7 @@ int tu104_init_hal(struct gk20a *g)
gops->gsp = tu104_ops_gsp;
gops->top = tu104_ops_top;
gops->grmgr = tu104_ops_grmgr;
gops->cic = tu104_ops_cic;
gops->cic_mon = tu104_ops_cic_mon;
gops->chip_init_gpu_characteristics = tu104_init_gpu_characteristics;
gops->get_litter_value = tu104_get_litter_value;
gops->semaphore_wakeup = nvgpu_channel_semaphore_wakeup;

2
drivers/gpu/nvgpu/hal/mc/mc_gm20b.c
View File

@@ -26,7 +26,7 @@
#include <nvgpu/atomic.h>
#include <nvgpu/io.h>
#include <nvgpu/mc.h>
#include <nvgpu/cic.h>
#include <nvgpu/cic_mon.h>
#include <nvgpu/ltc.h>
#include <nvgpu/gk20a.h>
#include <nvgpu/bug.h>

2
drivers/gpu/nvgpu/hal/mc/mc_gp10b_fusa.c
View File

@@ -25,7 +25,7 @@
#include <nvgpu/gk20a.h>
#include <nvgpu/io.h>
#include <nvgpu/mc.h>
#include <nvgpu/cic.h>
#include <nvgpu/cic_mon.h>
#include <nvgpu/engines.h>
#include <nvgpu/device.h>
#include <nvgpu/power_features/pg.h>

2
drivers/gpu/nvgpu/hal/mc/mc_gv100.c
View File

@@ -25,7 +25,7 @@
#include <nvgpu/types.h>
#include <nvgpu/io.h>
#include <nvgpu/mc.h>
#include <nvgpu/cic.h>
#include <nvgpu/cic_mon.h>
#include <nvgpu/gk20a.h>
#include <nvgpu/bug.h>
#include <nvgpu/engines.h>

2
drivers/gpu/nvgpu/hal/mc/mc_gv11b_fusa.c
View File

@@ -25,7 +25,7 @@
#include <nvgpu/types.h>
#include <nvgpu/io.h>
#include <nvgpu/mc.h>
#include <nvgpu/cic.h>
#include <nvgpu/cic_mon.h>
#include <nvgpu/gk20a.h>
#include <nvgpu/engines.h>

6
drivers/gpu/nvgpu/hal/mc/mc_intr_ga10b_fusa.c
View File

@@ -27,7 +27,7 @@
#include <nvgpu/engines.h>
#include <nvgpu/device.h>
#include <nvgpu/mc.h>
#include <nvgpu/cic.h>
#include <nvgpu/cic_mon.h>
#include <nvgpu/power_features/pg.h>
#include <nvgpu/gr/gr_instances.h>
@@ -204,7 +204,7 @@ void ga10b_intr_host2soc_0_unit_config(struct gk20a *g, u32 unit, bool enable)
u32 subtree = 0U;
u64 subtree_mask = 0ULL;
if (nvgpu_cic_intr_get_unit_info(g, unit, &subtree, &subtree_mask)
if (nvgpu_cic_mon_intr_get_unit_info(g, unit, &subtree, &subtree_mask)
== false) {
return;
}
@@ -500,7 +500,7 @@ void ga10b_intr_stall_unit_config(struct gk20a *g, u32 unit, bool enable)
unit = ga10b_intr_map_mc_stall_unit_to_intr_unit(g, unit);
if (nvgpu_cic_intr_get_unit_info(g, unit, &subtree, &subtree_mask)
if (nvgpu_cic_mon_intr_get_unit_info(g, unit, &subtree, &subtree_mask)
== false) {
return;
}

2
drivers/gpu/nvgpu/hal/mc/mc_tu104.c
View File

@@ -24,7 +24,7 @@
#include <nvgpu/io.h>
#include <nvgpu/utils.h>
#include <nvgpu/mc.h>
#include <nvgpu/cic.h>
#include <nvgpu/cic_mon.h>
#include <nvgpu/ltc.h>
#include <nvgpu/gk20a.h>
#include <nvgpu/engines.h>

6
drivers/gpu/nvgpu/hal/pmu/pmu_gk20a.c
View File

@@ -29,7 +29,7 @@
#include <nvgpu/pmu/fw.h>
#include <nvgpu/pmu/debug.h>
#include <nvgpu/pmu/pmu_pg.h>
#include <nvgpu/cic.h>
#include <nvgpu/cic_mon.h>
#include <nvgpu/mc.h>
#include <nvgpu/hw/gk20a/hw_pwr_gk20a.h>
@@ -449,7 +449,7 @@ void gk20a_pmu_enable_irq(struct nvgpu_pmu *pmu, bool enable)
nvgpu_log_fn(g, " ");
nvgpu_cic_intr_stall_unit_config(g, NVGPU_CIC_INTR_UNIT_PMU, NVGPU_CIC_INTR_DISABLE);
nvgpu_cic_mon_intr_stall_unit_config(g, NVGPU_CIC_INTR_UNIT_PMU, NVGPU_CIC_INTR_DISABLE);
nvgpu_falcon_set_irq(pmu->flcn, false, 0x0, 0x0);
@@ -465,7 +465,7 @@ void gk20a_pmu_enable_irq(struct nvgpu_pmu *pmu, bool enable)
pwr_falcon_irqmset_swgen0_f(1) |
pwr_falcon_irqmset_swgen1_f(1);
nvgpu_cic_intr_stall_unit_config(g, NVGPU_CIC_INTR_UNIT_PMU,
nvgpu_cic_mon_intr_stall_unit_config(g, NVGPU_CIC_INTR_UNIT_PMU,
NVGPU_CIC_INTR_ENABLE);
nvgpu_falcon_set_irq(pmu->flcn, true, intr_mask, intr_dest);

6
drivers/gpu/nvgpu/hal/pmu/pmu_gv11b_fusa.c
View File

@@ -27,7 +27,7 @@
#include <nvgpu/mm.h>
#include <nvgpu/gk20a.h>
#include <nvgpu/nvgpu_err.h>
#include <nvgpu/cic.h>
#include <nvgpu/cic_mon.h>
#include <nvgpu/firmware.h>
#include <nvgpu/bug.h>
#ifdef CONFIG_NVGPU_LS_PMU
@@ -447,7 +447,7 @@ void gv11b_pmu_enable_irq(struct nvgpu_pmu *pmu, bool enable)
nvgpu_log_fn(g, " ");
nvgpu_cic_intr_stall_unit_config(g, NVGPU_CIC_INTR_UNIT_PMU, NVGPU_CIC_INTR_DISABLE);
nvgpu_cic_mon_intr_stall_unit_config(g, NVGPU_CIC_INTR_UNIT_PMU, NVGPU_CIC_INTR_DISABLE);
nvgpu_falcon_set_irq(pmu->flcn, false, intr_mask, intr_dest);
@@ -467,7 +467,7 @@ void gv11b_pmu_enable_irq(struct nvgpu_pmu *pmu, bool enable)
#else
intr_mask = pwr_falcon_irqmset_ext_ecc_parity_f(1);
#endif
nvgpu_cic_intr_stall_unit_config(g, NVGPU_CIC_INTR_UNIT_PMU,
nvgpu_cic_mon_intr_stall_unit_config(g, NVGPU_CIC_INTR_UNIT_PMU,
NVGPU_CIC_INTR_ENABLE);
nvgpu_falcon_set_irq(pmu->flcn, true, intr_mask, intr_dest);

6
drivers/gpu/nvgpu/hal/priv_ring/priv_ring_gm20b_fusa.c
View File

@@ -29,7 +29,7 @@
#include <nvgpu/io.h>
#include <nvgpu/utils.h>
#include <nvgpu/power_features/cg.h>
#include <nvgpu/cic.h>
#include <nvgpu/cic_mon.h>
#include <nvgpu/mc.h>
#include "priv_ring_gm20b.h"
@@ -49,7 +49,7 @@ int gm20b_priv_ring_enable(struct gk20a *g)
#ifdef CONFIG_NVGPU_SIM
if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) {
nvgpu_log_info(g, "priv ring is already enabled");
nvgpu_cic_intr_stall_unit_config(g, NVGPU_CIC_INTR_UNIT_PRIV_RING,
nvgpu_cic_mon_intr_stall_unit_config(g, NVGPU_CIC_INTR_UNIT_PRIV_RING,
NVGPU_CIC_INTR_ENABLE);
return 0;
}
@@ -62,7 +62,7 @@ int gm20b_priv_ring_enable(struct gk20a *g)
/*
* Enable interrupt early on.
*/
nvgpu_cic_intr_stall_unit_config(g, NVGPU_CIC_INTR_UNIT_PRIV_RING,
nvgpu_cic_mon_intr_stall_unit_config(g, NVGPU_CIC_INTR_UNIT_PRIV_RING,
NVGPU_CIC_INTR_ENABLE);
nvgpu_writel(g, pri_ringmaster_command_r(),

117
drivers/gpu/nvgpu/include/nvgpu/cic.h → drivers/gpu/nvgpu/include/nvgpu/cic_mon.h
View File

@@ -20,14 +20,15 @@
* DEALINGS IN THE SOFTWARE.
*/
#ifndef NVGPU_CIC_H
#define NVGPU_CIC_H
#ifndef NVGPU_CIC_MON_H
#define NVGPU_CIC_MON_H
#include <nvgpu/types.h>
#include <nvgpu/static_analysis.h>
#include <nvgpu/log.h>
#if defined(CONFIG_NVGPU_NON_FUSA)
#define U32_BITS 32U
#define DIV_BY_U32_BITS(x) ((x) / U32_BITS)
#define MOD_BY_U32_BITS(x) ((x) % U32_BITS)
@@ -83,10 +84,10 @@
#define RUNLIST_INTR_TREE_0 0U
#define RUNLIST_INTR_TREE_1 1U
void nvgpu_cic_intr_unit_vectorid_init(struct gk20a *g, u32 unit, u32 *vectorid,
void nvgpu_cic_mon_intr_unit_vectorid_init(struct gk20a *g, u32 unit, u32 *vectorid,
u32 num_entries);
bool nvgpu_cic_intr_is_unit_info_valid(struct gk20a *g, u32 unit);
bool nvgpu_cic_intr_get_unit_info(struct gk20a *g, u32 unit, u32 *subtree,
bool nvgpu_cic_mon_intr_is_unit_info_valid(struct gk20a *g, u32 unit);
bool nvgpu_cic_mon_intr_get_unit_info(struct gk20a *g, u32 unit, u32 *subtree,
u64 *subtree_mask);
#endif
@@ -265,7 +266,9 @@ struct nvgpu_err_desc;
* struct.
*
*/
int nvgpu_cic_init_common(struct gk20a *g);
int nvgpu_cic_mon_setup(struct gk20a *g);
int nvgpu_cic_mon_init_lut(struct gk20a *g);
/**
* @brief De-initialize the CIC unit's data structures
@@ -284,7 +287,9 @@ int nvgpu_cic_init_common(struct gk20a *g);
*
* @retval None.
*/
int nvgpu_cic_deinit_common(struct gk20a *g);
int nvgpu_cic_mon_remove(struct gk20a *g);
int nvgpu_cic_mon_deinit_lut(struct gk20a *g);
int nvgpu_cic_mon_deinit(struct gk20a *g);
/**
* @brief Check if the input HW unit ID is valid CIC HW unit.
@@ -305,7 +310,7 @@ int nvgpu_cic_deinit_common(struct gk20a *g);
* @retval -EINVAL if CIC is not initialized and
* if input hw_unit_id is invalid.
*/
int nvgpu_cic_check_hw_unit_id(struct gk20a *g, u32 hw_unit_id);
int nvgpu_cic_mon_bound_check_hw_unit_id(struct gk20a *g, u32 hw_unit_id);
/**
* @brief Check if the input error ID is valid in CIC domain.
@@ -332,7 +337,7 @@ int nvgpu_cic_check_hw_unit_id(struct gk20a *g, u32 hw_unit_id);
* @retval -EINVAL if CIC is not initialized and
* if input hw_unit_id or err_id is invalid.
*/
int nvgpu_cic_check_err_id(struct gk20a *g, u32 hw_unit_id,
int nvgpu_cic_mon_bound_check_err_id(struct gk20a *g, u32 hw_unit_id,
u32 err_id);
/**
@@ -347,7 +352,7 @@ int nvgpu_cic_check_err_id(struct gk20a *g, u32 hw_unit_id,
* all the static data for each HW unit reporting error to CIC.
* - nvgpu_err_hw_module struct is inturn an array of struct
* nvgpu_err_desc which stores static data per error ID.
* - Use the nvgpu_cic_check_err_id() API to
* - Use the nvgpu_cic_mon_bound_check_err_id() API to
* - Check if the CIC unit is initialized so that the LUT is
* available to read the static data for input err_id.
* - Check if input HW unit ID and error ID are valid.
@@ -364,7 +369,7 @@ int nvgpu_cic_check_err_id(struct gk20a *g, u32 hw_unit_id,
* @retval -EINVAL if CIC is not initialized and
* if input hw_unit_id or err_id is invalid.
*/
int nvgpu_cic_get_err_desc(struct gk20a *g, u32 hw_unit_id,
int nvgpu_cic_mon_get_err_desc(struct gk20a *g, u32 hw_unit_id,
u32 err_id, struct nvgpu_err_desc **err_desc);
/**
@@ -390,7 +395,7 @@ int nvgpu_cic_get_err_desc(struct gk20a *g, u32 hw_unit_id,
* @retval -EAGAIN if SDL not initialized.
* @retval -ENOMEM if sufficient memory is not available.
*/
int nvgpu_cic_report_err_safety_services(struct gk20a *g,
int nvgpu_cic_mon_report_err_safety_services(struct gk20a *g,
void *err_info, size_t err_size, bool is_critical);
/**
@@ -407,7 +412,7 @@ int nvgpu_cic_report_err_safety_services(struct gk20a *g,
* < 0 otherwise.
* @retval -EINVAL if CIC is not initialized.
*/
int nvgpu_cic_get_num_hw_modules(struct gk20a *g);
int nvgpu_cic_mon_get_num_hw_modules(struct gk20a *g);
/**
* @brief Top half of stall interrupt ISR.
@@ -423,7 +428,7 @@ int nvgpu_cic_get_num_hw_modules(struct gk20a *g);
* @retval NVGPU_CIC_INTR_NONE if none of the stall interrupts are pending.
* @retval NVGPU_CIC_INTR_QUIESCE_PENDING if quiesce is pending.
*/
u32 nvgpu_cic_intr_stall_isr(struct gk20a *g);
u32 nvgpu_cic_mon_intr_stall_isr(struct gk20a *g);
/**
* @brief Bottom half of stall interrupt ISR.
@@ -433,7 +438,7 @@ u32 nvgpu_cic_intr_stall_isr(struct gk20a *g);
* This function is called to take action based on pending stall interrupts.
* The unit ISR functions are invoked based on triggered stall interrupts.
*/
void nvgpu_cic_intr_stall_handle(struct gk20a *g);
void nvgpu_cic_mon_intr_stall_handle(struct gk20a *g);
/**
* @brief Top half of nonstall interrupt ISR.
@@ -449,7 +454,7 @@ void nvgpu_cic_intr_stall_handle(struct gk20a *g);
* @retval NVGPU_CIC_INTR_NONE if none of the nonstall interrupts are pending.
* @retval NVGPU_CIC_INTR_QUIESCE_PENDING if quiesce is pending.
*/
u32 nvgpu_cic_intr_nonstall_isr(struct gk20a *g);
u32 nvgpu_cic_mon_intr_nonstall_isr(struct gk20a *g);
/**
* @brief Bottom half of nonstall interrupt ISR.
@@ -460,60 +465,7 @@ u32 nvgpu_cic_intr_nonstall_isr(struct gk20a *g);
* Based on triggered nonstall interrupts, this function will invoke
* nonstall operations.
*/
void nvgpu_cic_intr_nonstall_handle(struct gk20a *g);
/**
* @brief Wait for the stalling interrupts to complete.
*
* @param g [in] The GPU driver struct.
* @param timeout [in] Timeout
*
* Steps:
* - Get the stalling interrupts atomic count.
* - Wait for #timeout duration on the condition variable
* #sw_irq_stall_last_handled_cond until #sw_irq_stall_last_handled
* becomes greater than or equal to previously read stalling
* interrupt atomic count.
*
* @retval 0 if wait completes successfully.
* @retval -ETIMEDOUT if wait completes without stalling interrupts
* completing.
*/
int nvgpu_cic_wait_for_stall_interrupts(struct gk20a *g, u32 timeout);
/**
* @brief Wait for the non-stalling interrupts to complete.
*
* @param g [in] The GPU driver struct.
* @param timeout [in] Timeout
*
* Steps:
* - Get the non-stalling interrupts atomic count.
* - Wait for #timeout duration on the condition variable
* #sw_irq_nonstall_last_handled_cond until #sw_irq_nonstall_last_handled
* becomes greater than or equal to previously read non-stalling
* interrupt atomic count.
*
* @retval 0 if wait completes successfully.
* @retval -ETIMEDOUT if wait completes without nonstalling interrupts
* completing.
*/
int nvgpu_cic_wait_for_nonstall_interrupts(struct gk20a *g, u32 timeout);
/**
* @brief Wait for the interrupts to complete.
*
* @param g [in] The GPU driver struct.
*
* While freeing the channel or entering SW quiesce state, nvgpu driver needs
* to wait until all scheduled interrupt handlers have completed. This is
* because the interrupt handlers could access data structures after freeing.
* Steps:
* - Wait for stalling interrupts to complete with timeout disabled.
* - Wait for non-stalling interrupts to complete with timeout disabled.
*/
void nvgpu_cic_wait_for_deferred_interrupts(struct gk20a *g);
void nvgpu_cic_mon_intr_nonstall_handle(struct gk20a *g);
/**
* @brief Clear the GPU device interrupts at master level.
@@ -534,12 +486,7 @@ void nvgpu_cic_wait_for_deferred_interrupts(struct gk20a *g);
* - Write U32_MAX to the non-stalling interrupts enable clear register.
* - Release the spinlock g->mc.intr_lock.
*/
void nvgpu_cic_intr_mask(struct gk20a *g);
#ifdef CONFIG_NVGPU_NON_FUSA
void nvgpu_cic_log_pending_intrs(struct gk20a *g);
void nvgpu_cic_intr_enable(struct gk20a *g);
#endif
void nvgpu_cic_mon_intr_mask(struct gk20a *g);
/**
* @brief Enable/Disable the stalling interrupts for given GPU unit at the
@@ -581,7 +528,7 @@ void nvgpu_cic_intr_enable(struct gk20a *g);
* mc_intr_en_clear_r(#NVGPU_CIC_INTR_STALLING).
* - Release the spinlock g->mc.intr_lock.
*/
void nvgpu_cic_intr_stall_unit_config(struct gk20a *g, u32 unit, bool enable);
void nvgpu_cic_mon_intr_stall_unit_config(struct gk20a *g, u32 unit, bool enable);
/**
* @brief Enable/Disable the non-stalling interrupts for given GPU unit at the
@@ -623,7 +570,7 @@ void nvgpu_cic_intr_stall_unit_config(struct gk20a *g, u32 unit, bool enable);
* mc_intr_en_clear_r(#NVGPU_CIC_INTR_NONSTALLING).
* - Release the spinlock g->mc.intr_lock.
*/
void nvgpu_cic_intr_nonstall_unit_config(struct gk20a *g, u32 unit, bool enable);
void nvgpu_cic_mon_intr_nonstall_unit_config(struct gk20a *g, u32 unit, bool enable);
/**
* @brief Disable/Pause the stalling interrupts.
@@ -639,7 +586,7 @@ void nvgpu_cic_intr_nonstall_unit_config(struct gk20a *g, u32 unit, bool enable)
* (mc_intr_en_clear_r(#NVGPU_CIC_INTR_STALLING)).
* - Release the spinlock g->mc.intr_lock.
*/
void nvgpu_cic_intr_stall_pause(struct gk20a *g);
void nvgpu_cic_mon_intr_stall_pause(struct gk20a *g);
/**
* @brief Enable/Resume the stalling interrupts.
@@ -656,7 +603,7 @@ void nvgpu_cic_intr_stall_pause(struct gk20a *g);
* interrupts enable set register (mc_intr_en_set_r(#NVGPU_CIC_INTR_STALLING)).
* - Release the spinlock g->mc.intr_lock.
*/
void nvgpu_cic_intr_stall_resume(struct gk20a *g);
void nvgpu_cic_mon_intr_stall_resume(struct gk20a *g);
/**
* @brief Disable/Pause the non-stalling interrupts.
@@ -672,7 +619,7 @@ void nvgpu_cic_intr_stall_resume(struct gk20a *g);
* (mc_intr_en_clear_r(#NVGPU_CIC_INTR_NONSTALLING)).
* - Release the spinlock g->mc.intr_lock.
*/
void nvgpu_cic_intr_nonstall_pause(struct gk20a *g);
void nvgpu_cic_mon_intr_nonstall_pause(struct gk20a *g);
/**
* @brief Enable/Resume the non-stalling interrupts.
@@ -691,6 +638,10 @@ void nvgpu_cic_intr_nonstall_pause(struct gk20a *g);
* (mc_intr_en_set_r(#NVGPU_CIC_INTR_NONSTALLING)).
* - Release the spinlock g->mc.intr_lock.
*/
void nvgpu_cic_intr_nonstall_resume(struct gk20a *g);
void nvgpu_cic_mon_intr_nonstall_resume(struct gk20a *g);
#endif /* NVGPU_CIC_H */
#ifdef CONFIG_NVGPU_NON_FUSA
void nvgpu_cic_mon_intr_enable(struct gk20a *g);
#endif
#endif /* NVGPU_CIC_MON_H */

85
drivers/gpu/nvgpu/include/nvgpu/cic_rm.h Normal file
View File

@@ -0,0 +1,85 @@
/*
* Copyright (c) 2021, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef NVGPU_CIC_RM_H
#define NVGPU_CIC_RM_H
#include <nvgpu/log.h>
/**
* @brief Wait for the stalling interrupts to complete.
*
* @param g [in] The GPU driver struct.
* @param timeout [in] Timeout
*
* Steps:
* - Get the stalling interrupts atomic count.
* - Wait for #timeout duration on the condition variable
* #sw_irq_stall_last_handled_cond until #sw_irq_stall_last_handled
* becomes greater than or equal to previously read stalling
* interrupt atomic count.
*
* @retval 0 if wait completes successfully.
* @retval -ETIMEDOUT if wait completes without stalling interrupts
* completing.
*/
int nvgpu_cic_rm_wait_for_stall_interrupts(struct gk20a *g, u32 timeout);
/**
* @brief Wait for the non-stalling interrupts to complete.
*
* @param g [in] The GPU driver struct.
* @param timeout [in] Timeout
*
* Steps:
* - Get the non-stalling interrupts atomic count.
* - Wait for #timeout duration on the condition variable
* #sw_irq_nonstall_last_handled_cond until #sw_irq_nonstall_last_handled
* becomes greater than or equal to previously read non-stalling
* interrupt atomic count.
*
* @retval 0 if wait completes successfully.
* @retval -ETIMEDOUT if wait completes without nonstalling interrupts
* completing.
*/
int nvgpu_cic_rm_wait_for_nonstall_interrupts(struct gk20a *g, u32 timeout);
/**
* @brief Wait for the interrupts to complete.
*
* @param g [in] The GPU driver struct.
*
* While freeing the channel or entering SW quiesce state, nvgpu driver needs
* to wait until all scheduled interrupt handlers have completed. This is
* because the interrupt handlers could access data structures after freeing.
* Steps:
* - Wait for stalling interrupts to complete with timeout disabled.
* - Wait for non-stalling interrupts to complete with timeout disabled.
*/
void nvgpu_cic_rm_wait_for_deferred_interrupts(struct gk20a *g);
#ifdef CONFIG_NVGPU_NON_FUSA
void nvgpu_cic_rm_log_pending_intrs(struct gk20a *g);
#endif
#endif /* NVGPU_CIC_RM_H */

6
drivers/gpu/nvgpu/include/nvgpu/gk20a.h
View File

@@ -107,7 +107,7 @@ struct nvgpu_gpfifo_entry;
struct vm_gk20a_mapping_batch;
struct pmu_pg_stats_data;
struct clk_domains_mon_status_params;
struct nvgpu_cic;
struct nvgpu_cic_mon;
enum nvgpu_flush_op;
enum gk20a_mem_rw_flag;
@@ -796,8 +796,8 @@ struct gk20a {
/** Multi Instance GPU information. */
struct nvgpu_mig mig;
/** Pointer to struct storing CIC unit's data */
struct nvgpu_cic *cic;
/** Pointer to struct storing CIC-MON's data */
struct nvgpu_cic_mon *cic_mon;
};
/**

14
drivers/gpu/nvgpu/include/nvgpu/gops/cic.h → drivers/gpu/nvgpu/include/nvgpu/gops/cic_mon.h
View File

@@ -19,8 +19,8 @@
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef NVGPU_GOPS_CIC_H
#define NVGPU_GOPS_CIC_H
#ifndef NVGPU_GOPS_CIC_MON_H
#define NVGPU_GOPS_CIC_MON_H
#include <nvgpu/types.h>
@@ -31,14 +31,14 @@
*
*/
struct gk20a;
struct nvgpu_cic;
struct nvgpu_cic_mon;
/**
* CIC unit HAL operations
* CIC-MON unit HAL operations
*
* @see gpu_ops
*/
struct gops_cic {
struct gops_cic_mon {
/**
* @brief Chip specific CIC unit initialization.
*
@@ -47,7 +47,7 @@ struct gops_cic {
*
* @return 0 in case of success, < 0 in case of failure.
*/
int (*init)(struct gk20a *g, struct nvgpu_cic *cic);
int (*init)(struct gk20a *g, struct nvgpu_cic_mon *cic_mon);
/**
* @brief Report error to safety services.
@@ -64,4 +64,4 @@ struct gops_cic {
bool is_critical);
};
#endif/*NVGPU_GOPS_CIC_H*/
#endif/*NVGPU_GOPS_CIC_MON_H*/

4
drivers/gpu/nvgpu/include/nvgpu/gpu_ops.h
View File

@@ -71,7 +71,7 @@
#include <nvgpu/gops/pmu.h>
#include <nvgpu/gops/ecc.h>
#include <nvgpu/gops/grmgr.h>
#include <nvgpu/gops/cic.h>
#include <nvgpu/gops/cic_mon.h>
struct gk20a;
struct nvgpu_debug_context;
@@ -226,7 +226,7 @@ struct gpu_ops {
struct gops_grmgr grmgr;
struct gops_cic cic;
struct gops_cic_mon cic_mon;
};
#endif /* NVGPU_GOPS_OPS_H */

4
drivers/gpu/nvgpu/include/nvgpu/mc.h
View File

@@ -108,7 +108,7 @@
* + include/nvgpu/gops/mc.h
*
* Following interface is common function.
* + nvgpu_cic_wait_for_deferred_interrupts()
* + nvgpu_cic_rm_wait_for_deferred_interrupts()
*/
@@ -117,7 +117,7 @@
#include <nvgpu/atomic.h>
#include <nvgpu/lock.h>
#include <nvgpu/bitops.h>
#include <nvgpu/cic.h>
#include <nvgpu/cic_mon.h>
struct gk20a;
struct nvgpu_device;

4
drivers/gpu/nvgpu/os/linux/cic/cic_stub.c
View File

@@ -14,12 +14,12 @@
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include <nvgpu/cic.h>
#include <nvgpu/cic_mon.h>
#include <nvgpu/types.h>
struct gk20a;
int nvgpu_cic_report_err_safety_services(struct gk20a *g,
int nvgpu_cic_mon_report_err_safety_services(struct gk20a *g,
void *err_info, size_t err_size, bool is_critical)
{
return 0;

15
drivers/gpu/nvgpu/os/linux/module.c
View File

@@ -61,7 +61,8 @@
#include <nvgpu/cyclestats_snapshot.h>
#include <nvgpu/nvgpu_init.h>
#include <nvgpu/mc.h>
#include <nvgpu/cic.h>
#include <nvgpu/cic_mon.h>
#include <nvgpu/cic_rm.h>
#include "platform_gk20a.h"
#include "sysfs.h"
@@ -865,7 +866,7 @@ u64 nvgpu_resource_addr(struct platform_device *dev, int i)
static irqreturn_t gk20a_intr_isr_stall(int irq, void *dev_id)
{
struct gk20a *g = dev_id;
u32 err = nvgpu_cic_intr_stall_isr(g);
u32 err = nvgpu_cic_mon_intr_stall_isr(g);
return err == NVGPU_CIC_INTR_HANDLE ? IRQ_WAKE_THREAD : IRQ_NONE;
}
@@ -874,14 +875,14 @@ static irqreturn_t gk20a_intr_thread_isr_stall(int irq, void *dev_id)
{
struct gk20a *g = dev_id;
nvgpu_cic_intr_stall_handle(g);
nvgpu_cic_mon_intr_stall_handle(g);
return IRQ_HANDLED;
}
static irqreturn_t gk20a_intr_isr_nonstall(int irq, void *dev_id)
{
struct gk20a *g = dev_id;
u32 err = nvgpu_cic_intr_nonstall_isr(g);
u32 err = nvgpu_cic_mon_intr_nonstall_isr(g);
return err == NVGPU_CIC_INTR_HANDLE ? IRQ_WAKE_THREAD : IRQ_NONE;
}
@@ -890,7 +891,7 @@ static irqreturn_t gk20a_intr_thread_isr_nonstall(int irq, void *dev_id)
{
struct gk20a *g = dev_id;
nvgpu_cic_intr_nonstall_handle(g);
nvgpu_cic_mon_intr_nonstall_handle(g);
return IRQ_HANDLED;
}
@@ -1435,7 +1436,7 @@ int nvgpu_wait_for_gpu_idle(struct gk20a *g)
goto out;
}
nvgpu_cic_wait_for_deferred_interrupts(g);
nvgpu_cic_rm_wait_for_deferred_interrupts(g);
out:
return ret;
}
@@ -1454,7 +1455,7 @@ void gk20a_driver_start_unload(struct gk20a *g)
nvgpu_wait_for_idle(g);
nvgpu_cic_wait_for_deferred_interrupts(g);
nvgpu_cic_rm_wait_for_deferred_interrupts(g);
}
static inline void set_gk20a(struct platform_device *pdev, struct gk20a *gk20a)

11
drivers/gpu/nvgpu/os/linux/pci.c
View File

@@ -24,7 +24,8 @@
#include <nvgpu/nvgpu_common.h>
#include <nvgpu/kmem.h>
#include <nvgpu/mc.h>
#include <nvgpu/cic.h>
#include <nvgpu/cic_mon.h>
#include <nvgpu/cic_rm.h>
#include <nvgpu/enabled.h>
#include <nvgpu/errata.h>
#include <nvgpu/nvlink_probe.h>
@@ -326,8 +327,8 @@ static struct pci_device_id nvgpu_pci_table[] = {
static irqreturn_t nvgpu_pci_isr(int irq, void *dev_id)
{
struct gk20a *g = dev_id;
u32 ret_stall = nvgpu_cic_intr_stall_isr(g);
u32 ret_nonstall = nvgpu_cic_intr_nonstall_isr(g);
u32 ret_stall = nvgpu_cic_mon_intr_stall_isr(g);
u32 ret_nonstall = nvgpu_cic_mon_intr_nonstall_isr(g);
#if defined(CONFIG_PCI_MSI)
/* Send MSI EOI */
@@ -347,8 +348,8 @@ static irqreturn_t nvgpu_pci_intr_thread(int irq, void *dev_id)
{
struct gk20a *g = dev_id;
nvgpu_cic_intr_stall_handle(g);
nvgpu_cic_intr_nonstall_handle(g);
nvgpu_cic_mon_intr_stall_handle(g);
nvgpu_cic_mon_intr_nonstall_handle(g);
return IRQ_HANDLED;
}

4
drivers/gpu/nvgpu/os/posix/stubs.c
View File

@@ -27,7 +27,7 @@
#include <nvgpu/ecc.h>
#include <nvgpu/debugger.h>
#include <nvgpu/cic.h>
#include <nvgpu/cic_mon.h>
#include <nvgpu/types.h>
struct gk20a;
@@ -49,7 +49,7 @@ void nvgpu_ecc_sysfs_remove(struct gk20a *g)
}
#endif
int nvgpu_cic_report_err_safety_services(struct gk20a *g,
int nvgpu_cic_mon_report_err_safety_services(struct gk20a *g,
void *err_info, size_t err_size, bool is_critical)
{
return 0;

32
libs/dgpu/libnvgpu-drv-dgpu_safe.export
View File

@@ -527,13 +527,13 @@ nvgpu_ltc_remove_support
nvgpu_ltc_sync_enabled
nvgpu_local_golden_image_get_fault_injection
nvgpu_log_msg_impl
nvgpu_cic_intr_mask
nvgpu_cic_intr_nonstall_pause
nvgpu_cic_intr_nonstall_resume
nvgpu_cic_intr_nonstall_unit_config
nvgpu_cic_intr_stall_pause
nvgpu_cic_intr_stall_resume
nvgpu_cic_intr_stall_unit_config
nvgpu_cic_mon_intr_mask
nvgpu_cic_mon_intr_nonstall_pause
nvgpu_cic_mon_intr_nonstall_resume
nvgpu_cic_mon_intr_nonstall_unit_config
nvgpu_cic_mon_intr_stall_pause
nvgpu_cic_mon_intr_stall_resume
nvgpu_cic_mon_intr_stall_unit_config
nvgpu_mc_reset_dev
nvgpu_mc_reset_devtype
nvgpu_mc_reset_units
@@ -762,7 +762,7 @@ nvgpu_vm_put_buffers
nvgpu_vm_unmap
nvgpu_vmalloc_impl
nvgpu_vzalloc_impl
nvgpu_cic_wait_for_deferred_interrupts
nvgpu_cic_rm_wait_for_deferred_interrupts
nvgpu_worker_deinit
nvgpu_worker_enqueue
nvgpu_worker_init
@@ -793,10 +793,12 @@ nvgpu_init_pramin
gk20a_bus_set_bar0_window
nvgpu_pramin_ops_init
nvgpu_dma_alloc_vid_at
nvgpu_cic_init_common
nvgpu_cic_deinit_common
nvgpu_cic_check_hw_unit_id
nvgpu_cic_check_err_id
nvgpu_cic_get_err_desc
nvgpu_cic_report_err_safety_services
nvgpu_cic_get_num_hw_modules
nvgpu_cic_mon_setup
nvgpu_cic_mon_init_lut
nvgpu_cic_mon_deinit
nvgpu_cic_mon_bound_check_hw_unit_id
nvgpu_cic_mon_bound_check_err_id
nvgpu_cic_mon_get_err_desc
nvgpu_cic_mon_report_err_safety_services
nvgpu_cic_mon_get_num_hw_modules
nvgpu_cic_mon_remove

34
libs/igpu/libnvgpu-drv-igpu_safe.export
View File

@@ -248,7 +248,7 @@ gv11b_blcg_hshub_get_gating_prod
gv11b_netlist_is_firmware_defined
gv11b_top_get_num_lce
gv11b_bus_configure_debug_bus
gv11b_cic_init
gv11b_cic_mon_init
mc_gp10b_intr_stall_unit_config
mc_gp10b_intr_nonstall_unit_config
nvgpu_acr_bootstrap_hs_acr
@@ -544,13 +544,13 @@ nvgpu_ltc_remove_support
nvgpu_ltc_sync_enabled
nvgpu_local_golden_image_get_fault_injection
nvgpu_log_msg_impl
nvgpu_cic_intr_mask
nvgpu_cic_intr_nonstall_pause
nvgpu_cic_intr_nonstall_resume
nvgpu_cic_intr_nonstall_unit_config
nvgpu_cic_intr_stall_pause
nvgpu_cic_intr_stall_resume
nvgpu_cic_intr_stall_unit_config
nvgpu_cic_mon_intr_mask
nvgpu_cic_mon_intr_nonstall_pause
nvgpu_cic_mon_intr_nonstall_resume
nvgpu_cic_mon_intr_nonstall_unit_config
nvgpu_cic_mon_intr_stall_pause
nvgpu_cic_mon_intr_stall_resume
nvgpu_cic_mon_intr_stall_unit_config
nvgpu_mc_reset_dev
nvgpu_mc_reset_devtype
nvgpu_mc_reset_units
@@ -779,7 +779,7 @@ nvgpu_vm_put_buffers
nvgpu_vm_unmap
nvgpu_vmalloc_impl
nvgpu_vzalloc_impl
nvgpu_cic_wait_for_deferred_interrupts
nvgpu_cic_rm_wait_for_deferred_interrupts
nvgpu_worker_deinit
nvgpu_worker_enqueue
nvgpu_worker_init
@@ -808,10 +808,12 @@ nvgpu_rc_tsg_and_related_engines
nvgpu_rc_mmu_fault
gp10b_priv_ring_isr_handle_0
gp10b_priv_ring_isr_handle_1
nvgpu_cic_init_common
nvgpu_cic_deinit_common
nvgpu_cic_check_hw_unit_id
nvgpu_cic_check_err_id
nvgpu_cic_get_err_desc
nvgpu_cic_report_err_safety_services
nvgpu_cic_get_num_hw_modules
nvgpu_cic_mon_setup
nvgpu_cic_mon_init_lut
nvgpu_cic_mon_deinit
nvgpu_cic_mon_bound_check_hw_unit_id
nvgpu_cic_mon_bound_check_err_id
nvgpu_cic_mon_get_err_desc
nvgpu_cic_mon_report_err_safety_services
nvgpu_cic_mon_get_num_hw_modules
nvgpu_cic_mon_remove

9
userspace/units/acr/nvgpu-acr.c
View File

@@ -35,7 +35,7 @@
#include <nvgpu/firmware.h>
#include <nvgpu/netlist.h>
#include <nvgpu/fuse.h>
#include <nvgpu/cic.h>
#include <nvgpu/cic_mon.h>
#include <nvgpu/gr/gr.h>
@@ -219,11 +219,16 @@ static int init_acr_falcon_test_env(struct unit_module *m, struct gk20a *g)
return -ENODEV;
}
err = nvgpu_cic_init_common(g);
err = nvgpu_cic_mon_setup(g);
if (err != 0) {
unit_return_fail(m, "CIC init failed\n");
}
err = nvgpu_cic_mon_init_lut(g);
if (err != 0) {
unit_return_fail(m, "CIC LUT init failed\n");
}
/*
* Register space: FB_MMU
*/

16
userspace/units/bus/nvgpu-bus.c
View File

@@ -25,7 +25,7 @@
#include <nvgpu/posix/io.h>
#include <unit/core.h>
#include <nvgpu/io.h>
#include <nvgpu/cic.h>
#include <nvgpu/cic_mon.h>
#include <os/posix/os_posix.h>
#include <nvgpu/posix/posix-fault-injection.h>
@@ -36,7 +36,7 @@
#include <hal/bus/bus_gm20b.h>
#include <hal/bus/bus_gp10b.h>
#include <hal/bus/bus_gv11b.h>
#include <hal/cic/cic_gv11b.h>
#include <hal/cic/mon/cic_gv11b.h>
#include <nvgpu/hw/gv11b/hw_mc_gv11b.h>
#include <nvgpu/hw/gv11b/hw_bus_gv11b.h>
@@ -130,8 +130,8 @@ int test_bus_setup(struct unit_module *m, struct gk20a *g, void *args)
g->ops.mc.intr_nonstall_unit_config =
mc_gp10b_intr_nonstall_unit_config;
g->ops.ptimer.isr = gk20a_ptimer_isr;
g->ops.cic.init = gv11b_cic_init;
g->ops.cic.report_err = nvgpu_cic_report_err_safety_services;
g->ops.cic_mon.init = gv11b_cic_mon_init;
g->ops.cic_mon.report_err = nvgpu_cic_mon_report_err_safety_services;
/* Map register space NV_PRIV_MASTER */
if (nvgpu_posix_io_add_reg_space(g, NV_PBUS_START, NV_PBUS_SIZE) != 0) {
@@ -158,12 +158,18 @@ int test_bus_setup(struct unit_module *m, struct gk20a *g, void *args)
(void)nvgpu_posix_register_io(g, &test_reg_callbacks);
if (nvgpu_cic_init_common(g) != 0) {
if (nvgpu_cic_mon_setup(g) != 0) {
unit_err(m, "%s: Failed to initialize CIC\n",
__func__);
return UNIT_FAIL;
}
if (nvgpu_cic_mon_init_lut(g) != 0) {
unit_err(m, "%s: Failed to initialize CIC LUT\n",
__func__);
return UNIT_FAIL;
}
return UNIT_SUCCESS;
}

16
userspace/units/ce/nvgpu-ce.c
View File

@@ -27,10 +27,10 @@
#include <nvgpu/gk20a.h>
#include <nvgpu/device.h>
#include <nvgpu/ce.h>
#include <nvgpu/cic.h>
#include <nvgpu/cic_mon.h>
#include <hal/ce/ce_gp10b.h>
#include <hal/ce/ce_gv11b.h>
#include <hal/cic/cic_gv11b.h>
#include <hal/cic/mon/cic_gv11b.h>
#include <nvgpu/hw/gv11b/hw_ce_gv11b.h>
#include "nvgpu-ce.h"
@@ -128,15 +128,21 @@ int test_ce_setup_env(struct unit_module *m,
g->blcg_enabled = false;
nvgpu_spinlock_init(&g->mc.intr_lock);
g->ops.cic.init = gv11b_cic_init;
g->ops.cic.report_err = nvgpu_cic_report_err_safety_services;
g->ops.cic_mon.init = gv11b_cic_mon_init;
g->ops.cic_mon.report_err = nvgpu_cic_mon_report_err_safety_services;
if (nvgpu_cic_init_common(g) != 0) {
if (nvgpu_cic_mon_setup(g) != 0) {
unit_err(m, "%s: failed to initialize CIC\n",
__func__);
return UNIT_FAIL;
}
if (nvgpu_cic_mon_init_lut(g) != 0) {
unit_err(m, "%s: failed to initialize CIC LUT\n",
__func__);
return UNIT_FAIL;
}
return UNIT_SUCCESS;
}

14
userspace/units/fb/fb_gv11b_fusa.c
View File

@@ -27,7 +27,7 @@
#include <nvgpu/gk20a.h>
#include <nvgpu/io.h>
#include <nvgpu/cic.h>
#include <nvgpu/cic_mon.h>
#include <nvgpu/nvgpu_init.h>
#include "hal/mc/mc_gp10b.h"
#include "hal/fb/fb_gm20b.h"
@@ -35,7 +35,7 @@
#include "hal/fb/ecc/fb_ecc_gv11b.h"
#include "hal/fb/intr/fb_intr_gv11b.h"
#include "hal/fb/intr/fb_intr_ecc_gv11b.h"
#include "hal/cic/cic_gv11b.h"
#include "hal/cic/mon/cic_gv11b.h"
#include <nvgpu/hw/gv11b/hw_fb_gv11b.h>
#include "fb_fusa.h"
@@ -64,8 +64,8 @@ int fb_gv11b_init_test(struct unit_module *m, struct gk20a *g, void *args)
g->ops.mc.intr_nonstall_unit_config =
mc_gp10b_intr_nonstall_unit_config;
g->ops.fb.intr.enable = gv11b_fb_intr_enable;
g->ops.cic.init = gv11b_cic_init;
g->ops.cic.report_err = nvgpu_cic_report_err_safety_services;
g->ops.cic_mon.init = gv11b_cic_mon_init;
g->ops.cic_mon.report_err = nvgpu_cic_mon_report_err_safety_services;
/*
* Define some arbitrary addresses for test purposes.
@@ -78,10 +78,14 @@ int fb_gv11b_init_test(struct unit_module *m, struct gk20a *g, void *args)
g->mm.mmu_rd_mem.cpu_va = (void *) 0x30000000;
g->mm.mmu_rd_mem.aperture = APERTURE_SYSMEM;
if (nvgpu_cic_init_common(g) != 0) {
if (nvgpu_cic_mon_setup(g) != 0) {
unit_return_fail(m, "CIC init failed\n");
}
if (nvgpu_cic_mon_init_lut(g) != 0) {
unit_return_fail(m, "CIC LUT init failed\n");
}
g->ops.ecc.ecc_init_support(g);
nvgpu_writel(g, fb_niso_intr_en_set_r(0), 0);

9
userspace/units/fifo/nvgpu-fifo-common.c
View File

@@ -32,7 +32,7 @@
#include <nvgpu/fifo/userd.h>
#include <nvgpu/gk20a.h>
#include <nvgpu/device.h>
#include <nvgpu/cic.h>
#include <nvgpu/cic_mon.h>
#include <nvgpu/posix/io.h>
@@ -188,12 +188,17 @@ int test_fifo_init_support(struct unit_module *m, struct gk20a *g, void *args)
/* Do not allocate from vidmem */
nvgpu_set_enabled(g, NVGPU_MM_UNIFIED_MEMORY, true);
err = nvgpu_cic_init_common(g);
err = nvgpu_cic_mon_setup(g);
if (err != 0) {
unit_err(m, "CIC init failed!\n");
return UNIT_FAIL;
}
err = nvgpu_cic_mon_init_lut(g);
if (err != 0) {
unit_return_fail(m, "CIC LUT init failed\n");
}
return UNIT_SUCCESS;
fail:

15
userspace/units/gr/nvgpu-gr.c
View File

@@ -33,12 +33,12 @@
#include <nvgpu/netlist.h>
#include <nvgpu/gr/gr.h>
#include <nvgpu/gr/gr_falcon.h>
#include <nvgpu/cic.h>
#include <nvgpu/cic_mon.h>
#include "common/gr/gr_falcon_priv.h"
#include "hal/init/hal_gv11b.h"
#include "hal/cic/cic_gv11b.h"
#include "hal/cic/mon/cic_gv11b.h"
#include "nvgpu-gr.h"
#include "nvgpu-gr-gv11b.h"
@@ -167,14 +167,19 @@ int test_gr_init_setup_ready(struct unit_module *m,
nvgpu_device_init(g);
nvgpu_fifo_setup_sw(g);
g->ops.cic.init = gv11b_cic_init;
g->ops.cic.report_err = nvgpu_cic_report_err_safety_services;
g->ops.cic_mon.init = gv11b_cic_mon_init;
g->ops.cic_mon.report_err = nvgpu_cic_mon_report_err_safety_services;
err = nvgpu_cic_init_common(g);
err = nvgpu_cic_mon_setup(g);
if (err != 0) {
unit_return_fail(m, "CIC init failed\n");
}
err = nvgpu_cic_mon_init_lut(g);
if (err != 0) {
unit_return_fail(m, "CIC LUT init failed\n");
}
/* Allocate and Initialize GR */
err = test_gr_init_setup(m, g, args);
if (err != 0) {

9
userspace/units/ltc/nvgpu-ltc.c
View File

@@ -37,7 +37,7 @@
#include <nvgpu/nvgpu_mem.h>
#include <nvgpu/ecc.h>
#include <nvgpu/netlist.h>
#include <nvgpu/cic.h>
#include <nvgpu/cic_mon.h>
#include <nvgpu/gr/gr.h>
#include <hal/ltc/intr/ltc_intr_gv11b.h>
#include <nvgpu/vm.h>
@@ -137,11 +137,16 @@ int test_ltc_init_support(struct unit_module *m,
unit_return_fail(m, "nvgpu_init_hal failed\n");
}
err = nvgpu_cic_init_common(g);
err = nvgpu_cic_mon_setup(g);
if (err != 0) {
unit_return_fail(m, "CIC init failed\n");
}
err = nvgpu_cic_mon_init_lut(g);
if (err != 0) {
unit_return_fail(m, "CIC LUT init failed\n");
}
/*
* Init dependent ECC unit
*/

37
userspace/units/mc/nvgpu-mc.c
View File

@@ -26,7 +26,8 @@
#include <nvgpu/gk20a.h>
#include <nvgpu/mc.h>
#include <nvgpu/cic.h>
#include <nvgpu/cic_mon.h>
#include <nvgpu/cic_rm.h>
#include <nvgpu/hal_init.h>
#include <nvgpu/device.h>
#include <nvgpu/engines.h>
@@ -284,7 +285,7 @@ int test_unit_config(struct unit_module *m, struct gk20a *g, void *args)
unit = mc_units[i].num;
/* enable stall intr */
nvgpu_cic_intr_stall_unit_config(g, unit, true);
nvgpu_cic_mon_intr_stall_unit_config(g, unit, true);
val = nvgpu_posix_io_readl_reg_space(g, STALL_EN_REG);
if (val != mc_units[i].bit) {
unit_return_fail(m, "failed to enable stall intr for unit %u val=0x%08x\n",
@@ -292,7 +293,7 @@ int test_unit_config(struct unit_module *m, struct gk20a *g, void *args)
}
/* disable stall intr */
nvgpu_cic_intr_stall_unit_config(g, unit, false);
nvgpu_cic_mon_intr_stall_unit_config(g, unit, false);
val = nvgpu_posix_io_readl_reg_space(g, STALL_DIS_REG);
if (val != mc_units[i].bit) {
unit_return_fail(m, "failed to disable stall intr for unit %u val=0x%08x\n",
@@ -300,7 +301,7 @@ int test_unit_config(struct unit_module *m, struct gk20a *g, void *args)
}
/* enable nonstall intr */
nvgpu_cic_intr_nonstall_unit_config(g, unit, true);
nvgpu_cic_mon_intr_nonstall_unit_config(g, unit, true);
val = nvgpu_posix_io_readl_reg_space(g, NONSTALL_EN_REG);
if (val != mc_units[i].bit) {
unit_return_fail(m, "failed to enable nonstall intr for unit %u val=0x%08x\n",
@@ -308,7 +309,7 @@ int test_unit_config(struct unit_module *m, struct gk20a *g, void *args)
}
/* disable stall intr */
nvgpu_cic_intr_nonstall_unit_config(g, unit, false);
nvgpu_cic_mon_intr_nonstall_unit_config(g, unit, false);
val = nvgpu_posix_io_readl_reg_space(g, NONSTALL_DIS_REG);
if (val != mc_units[i].bit) {
unit_return_fail(m, "failed to disable nonstall intr for unit %u val=0x%08x\n",
@@ -318,7 +319,7 @@ int test_unit_config(struct unit_module *m, struct gk20a *g, void *args)
/* negative testing - invalid unit - stall */
nvgpu_posix_io_writel_reg_space(g, STALL_EN_REG, 0x0); /* clear reg */
nvgpu_cic_intr_stall_unit_config(g, U32_MAX, true);
nvgpu_cic_mon_intr_stall_unit_config(g, U32_MAX, true);
val = nvgpu_posix_io_readl_reg_space(g, STALL_EN_REG);
if (val != 0U) {
unit_return_fail(m, "Incorrectly enabled interrupt for invalid unit, val=0x%08x\n",
@@ -327,7 +328,7 @@ int test_unit_config(struct unit_module *m, struct gk20a *g, void *args)
/* negative testing - invalid unit - nonstall */
nvgpu_posix_io_writel_reg_space(g, NONSTALL_EN_REG, 0x0); /* clear reg */
nvgpu_cic_intr_nonstall_unit_config(g, U32_MAX, true);
nvgpu_cic_mon_intr_nonstall_unit_config(g, U32_MAX, true);
val = nvgpu_posix_io_readl_reg_space(g, NONSTALL_EN_REG);
if (val != 0U) {
unit_return_fail(m, "Incorrectly enabled interrupt for invalid unit, val=0x%08x\n",
@@ -355,18 +356,18 @@ int test_pause_resume_mask(struct unit_module *m, struct gk20a *g, void *args)
g->mc.intr_mask_restore[1] = 0U;
/* enable something to pause and resume */
nvgpu_cic_intr_stall_unit_config(g, NVGPU_CIC_INTR_UNIT_PRIV_RING, true);
nvgpu_cic_intr_nonstall_unit_config(g, NVGPU_CIC_INTR_UNIT_BUS, true);
nvgpu_cic_mon_intr_stall_unit_config(g, NVGPU_CIC_INTR_UNIT_PRIV_RING, true);
nvgpu_cic_mon_intr_nonstall_unit_config(g, NVGPU_CIC_INTR_UNIT_BUS, true);
/* pause stall */
nvgpu_cic_intr_stall_pause(g);
nvgpu_cic_mon_intr_stall_pause(g);
val = nvgpu_posix_io_readl_reg_space(g, STALL_DIS_REG);
if (val != U32_MAX) {
unit_return_fail(m, "failed to pause stall intr\n");
}
/* pause nonstall */
nvgpu_cic_intr_nonstall_pause(g);
nvgpu_cic_mon_intr_nonstall_pause(g);
val = nvgpu_posix_io_readl_reg_space(g, NONSTALL_DIS_REG);
if (val != U32_MAX) {
unit_return_fail(m, "failed to pause nonstall intr\n");
@@ -374,7 +375,7 @@ int test_pause_resume_mask(struct unit_module *m, struct gk20a *g, void *args)
/* resume stall */
nvgpu_posix_io_writel_reg_space(g, STALL_EN_REG, 0x0);
nvgpu_cic_intr_stall_resume(g);
nvgpu_cic_mon_intr_stall_resume(g);
val = nvgpu_posix_io_readl_reg_space(g, STALL_EN_REG);
if (val != expected_stall_val) {
unit_return_fail(m, "failed to resume stall intr\n");
@@ -382,7 +383,7 @@ int test_pause_resume_mask(struct unit_module *m, struct gk20a *g, void *args)
/* resume nonstall */
nvgpu_posix_io_writel_reg_space(g, NONSTALL_EN_REG, 0x0);
nvgpu_cic_intr_nonstall_resume(g);
nvgpu_cic_mon_intr_nonstall_resume(g);
val = nvgpu_posix_io_readl_reg_space(g, NONSTALL_EN_REG);
if (val != expected_nonstall_val) {
unit_return_fail(m, "failed to resume nonstall intr\n");
@@ -393,7 +394,7 @@ int test_pause_resume_mask(struct unit_module *m, struct gk20a *g, void *args)
nvgpu_posix_io_writel_reg_space(g, NONSTALL_DIS_REG, 0x0);
/* mask all */
nvgpu_cic_intr_mask(g);
nvgpu_cic_mon_intr_mask(g);
val = nvgpu_posix_io_readl_reg_space(g, STALL_DIS_REG);
if (val != U32_MAX) {
unit_return_fail(m, "failed to mask stall intr\n");
@@ -406,7 +407,7 @@ int test_pause_resume_mask(struct unit_module *m, struct gk20a *g, void *args)
/* make this HAL NULL for branch coverage */
save_func = g->ops.mc.intr_mask;
g->ops.mc.intr_mask = NULL;
nvgpu_cic_intr_mask(g);
nvgpu_cic_mon_intr_mask(g);
g->ops.mc.intr_mask = save_func;
return UNIT_SUCCESS;
@@ -664,18 +665,18 @@ int test_wait_for_deferred_interrupts(struct unit_module *m, struct gk20a *g,
/* immediate completion */
nvgpu_atomic_set(&g->mc.sw_irq_stall_pending, 0);
nvgpu_atomic_set(&g->mc.sw_irq_nonstall_pending, 0);
nvgpu_cic_wait_for_deferred_interrupts(g);
nvgpu_cic_rm_wait_for_deferred_interrupts(g);
/* cause timeout */
nvgpu_posix_enable_fault_injection(cond_fi, true, 0);
/* wait on stall until timeout for branch coverage */
nvgpu_atomic_set(&g->mc.sw_irq_stall_pending, 1);
nvgpu_cic_wait_for_deferred_interrupts(g);
nvgpu_cic_rm_wait_for_deferred_interrupts(g);
/* wait on nonstall until timeout for branch coverage */
nvgpu_atomic_set(&g->mc.sw_irq_nonstall_pending, 1);
nvgpu_cic_wait_for_deferred_interrupts(g);
nvgpu_cic_rm_wait_for_deferred_interrupts(g);
/* disable the fault injection */
nvgpu_posix_enable_fault_injection(cond_fi, false, 0);

24
userspace/units/mc/nvgpu-mc.h
View File

@@ -74,12 +74,12 @@ int test_mc_free_env(struct unit_module *m, struct gk20a *g, void *args);
/**
* Test specification for: test_unit_config
*
* Description: Validate function of nvgpu_cic_intr_stall_unit_config and
* nvgpu_cic_intr_nonstall_unit_config.
* Description: Validate function of nvgpu_cic_mon_intr_stall_unit_config and
* nvgpu_cic_mon_intr_nonstall_unit_config.
*
* Test Type: Feature, Error guessing
*
* Targets: nvgpu_cic_intr_stall_unit_config, nvgpu_cic_intr_nonstall_unit_config,
* Targets: nvgpu_cic_mon_intr_stall_unit_config, nvgpu_cic_mon_intr_nonstall_unit_config,
* mc_gp10b_intr_stall_unit_config, mc_gp10b_intr_nonstall_unit_config
*
* Input: test_mc_setup_env must have been run.
@@ -88,22 +88,22 @@ int test_mc_free_env(struct unit_module *m, struct gk20a *g, void *args);
* - Set each of the mock registers for enabling & disabling the stall &
* non-stall interrupts to 0.
* - Loop through table of units:
* - Call nvgpu_cic_intr_stall_unit_config for the unit to enable the stall
* - Call nvgpu_cic_mon_intr_stall_unit_config for the unit to enable the stall
* interrupt.
* - Verify the stall interrupt enable register has the bit set for the unit.
* - Call nvgpu_cic_intr_stall_unit_config for the unit to disable the interrupt.
* - Call nvgpu_cic_mon_intr_stall_unit_config for the unit to disable the interrupt.
* - Verify the stall interrupt disable register has the bit set for the unit.
* - Call nvgpu_cic_intr_nonstall_unit_config for the unit to enable the
* - Call nvgpu_cic_mon_intr_nonstall_unit_config for the unit to enable the
* non-stall interrupt.
* - Verify the non-stall interrupt enable register has the bit set for the unit.
* - Call nvgpu_cic_intr_nonstall_unit_config for the unit to disable the interrupt.
* - Call nvgpu_cic_mon_intr_nonstall_unit_config for the unit to disable the interrupt.
* - Verify the non-stall interrupt disable register has the bit set for the unit.
* - Clear the stall enable register.
* - For negative testing, call nvgpu_cic_intr_stall_unit_config() with an
* - For negative testing, call nvgpu_cic_mon_intr_stall_unit_config() with an
* invalid unit number, and verify no bits are set in the stall interrupt
* enable register.
* - Clear the stall enable register.
* - For negative testing, call nvgpu_cic_intr_nonstall_unit_config() with an
* - For negative testing, call nvgpu_cic_mon_intr_nonstall_unit_config() with an
* invalid unit number, and verify no bits are set in the non-stall interrupt
* enable register.
*
@@ -118,9 +118,9 @@ int test_unit_config(struct unit_module *m, struct gk20a *g, void *args);
*
* Test Type: Feature
*
* Targets: nvgpu_cic_intr_stall_pause, nvgpu_cic_intr_stall_resume,
* nvgpu_cic_intr_nonstall_pause, nvgpu_cic_intr_nonstall_resume,
* nvgpu_cic_intr_mask, mc_gp10b_intr_stall_pause,
* Targets: nvgpu_cic_mon_intr_stall_pause, nvgpu_cic_mon_intr_stall_resume,
* nvgpu_cic_mon_intr_nonstall_pause, nvgpu_cic_mon_intr_nonstall_resume,
* nvgpu_cic_mon_intr_mask, mc_gp10b_intr_stall_pause,
* mc_gp10b_intr_stall_resume, mc_gp10b_intr_nonstall_pause,
* mc_gp10b_intr_nonstall_resume, mc_gp10b_intr_mask
*

14
userspace/units/mm/hal/mmu_fault/gv11b_fusa/mmu-fault-gv11b-fusa.c
View File

@@ -37,7 +37,7 @@
#include <nvgpu/tsg.h>
#include <nvgpu/engines.h>
#include <nvgpu/preempt.h>
#include <nvgpu/cic.h>
#include <nvgpu/cic_mon.h>
#include <nvgpu/nvgpu_init.h>
#include <nvgpu/hw/gv11b/hw_fb_gv11b.h>
#include <nvgpu/hw/gv11b/hw_gmmu_gv11b.h>
@@ -61,7 +61,7 @@
#include "hal/mm/gmmu/gmmu_gv11b.h"
#include "hal/mm/mm_gp10b.h"
#include "hal/mm/mm_gv11b.h"
#include "hal/cic/cic_gv11b.h"
#include "hal/cic/mon/cic_gv11b.h"
#include "hal/mm/mmu_fault/mmu_fault_gv11b.h"
#include "mmu-fault-gv11b-fusa.h"
@@ -222,13 +222,17 @@ int test_env_init_mm_mmu_fault_gv11b_fusa(struct unit_module *m,
unit_return_fail(m, "nvgpu_init_mm_support failed\n");
}
g->ops.cic.init = gv11b_cic_init;
g->ops.cic.report_err = nvgpu_cic_report_err_safety_services;
g->ops.cic_mon.init = gv11b_cic_mon_init;
g->ops.cic_mon.report_err = nvgpu_cic_mon_report_err_safety_services;
if (nvgpu_cic_init_common(g) != 0) {
if (nvgpu_cic_mon_setup(g) != 0) {
unit_return_fail(m, "Failed to initialize CIC\n");
}
if (nvgpu_cic_mon_init_lut(g) != 0) {
unit_return_fail(m, "Failed to initialize CIC LUT\n");
}
return UNIT_SUCCESS;
}

16
userspace/units/priv_ring/nvgpu-priv_ring.c
View File

@@ -23,14 +23,14 @@
#include <unit/unit.h>
#include <unit/io.h>
#include <nvgpu/posix/io.h>
#include <nvgpu/cic.h>
#include <nvgpu/cic_mon.h>
#include <nvgpu/gk20a.h>
#include <hal/priv_ring/priv_ring_gm20b.h>
#include <hal/priv_ring/priv_ring_gp10b.h>
#include <hal/init/hal_gv11b_litter.h>
#include <hal/mc/mc_gp10b.h>
#include "hal/cic/cic_gv11b.h"
#include "hal/cic/mon/cic_gv11b.h"
#include <nvgpu/hw/gv11b/hw_pri_ringstation_sys_gv11b.h>
#include <nvgpu/hw/gv11b/hw_pri_ringstation_gpc_gv11b.h>
@@ -125,8 +125,8 @@ int test_priv_ring_setup(struct unit_module *m, struct gk20a *g, void *args)
g->ops.get_litter_value = gv11b_get_litter_value;
g->ops.mc.intr_stall_unit_config =
mc_gp10b_intr_stall_unit_config;
g->ops.cic.init = gv11b_cic_init;
g->ops.cic.report_err = nvgpu_cic_report_err_safety_services;
g->ops.cic_mon.init = gv11b_cic_mon_init;
g->ops.cic_mon.report_err = nvgpu_cic_mon_report_err_safety_services;
/* Map register space NV_PRIV_MASTER */
if (nvgpu_posix_io_add_reg_space(g, NV_PRIV_MASTER_START,
@@ -162,12 +162,18 @@ int test_priv_ring_setup(struct unit_module *m, struct gk20a *g, void *args)
(void)nvgpu_posix_register_io(g, &test_reg_callbacks);
if (nvgpu_cic_init_common(g) != 0) {
if (nvgpu_cic_mon_setup(g) != 0) {
unit_err(m, "%s: Failed to initialize CIC\n",
__func__);
return UNIT_FAIL;
}
if (nvgpu_cic_mon_init_lut(g) != 0) {
unit_err(m, "%s: Failed to initialize CIC LUT\n",
__func__);
return UNIT_FAIL;
}
return UNIT_SUCCESS;
}

16
userspace/units/ptimer/nvgpu-ptimer.c
View File

@@ -26,9 +26,9 @@
#include <nvgpu/gk20a.h>
#include <nvgpu/ptimer.h>
#include <nvgpu/cic.h>
#include <nvgpu/cic_mon.h>
#include <hal/ptimer/ptimer_gk20a.h>
#include <hal/cic/cic_gv11b.h>
#include <hal/cic/mon/cic_gv11b.h>
#include <nvgpu/hw/gk20a/hw_timer_gk20a.h>
#include "nvgpu-ptimer.h"
@@ -90,8 +90,8 @@ int test_setup_env(struct unit_module *m,
g->ops.ptimer.read_ptimer = gk20a_read_ptimer;
g->ops.ptimer.isr = gk20a_ptimer_isr;
g->ops.cic.init = gv11b_cic_init;
g->ops.cic.report_err = nvgpu_cic_report_err_safety_services;
g->ops.cic_mon.init = gv11b_cic_mon_init;
g->ops.cic_mon.report_err = nvgpu_cic_mon_report_err_safety_services;
/* Create ptimer register space */
if (nvgpu_posix_io_add_reg_space(g, PTIMER_REG_SPACE_START,
@@ -102,12 +102,18 @@ int test_setup_env(struct unit_module *m,
}
(void)nvgpu_posix_register_io(g, &test_reg_callbacks);
if (nvgpu_cic_init_common(g) != 0) {
if (nvgpu_cic_mon_setup(g) != 0) {
unit_err(m, "%s: failed to initialize CIC\n",
__func__);
return UNIT_FAIL;
}
if (nvgpu_cic_mon_init_lut(g) != 0) {
unit_err(m, "%s: failed to initialize CIC LUT\n",
__func__);
return UNIT_FAIL;
}
return UNIT_SUCCESS;
}