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0526e7eaa9
common.cic unit is divided into common.cic.mon and common.cic.rm based on rm and mon process split. CIC-mon subunit includes the code which is utilized in critical interrupt handling path like initialization, error detection and error reporting path. CIC-rm subunit includes the code corresponding to rest of interrupt handling(like collecting error debug data from registers) and ISR status management (status of deferred interrupts). Split the CIC APIs and data-members into above two subunits. JIRA NVGPU-6899 Change-Id: I151b59105ff570607c4a62e974785e9c1323ef69 Signed-off-by: Tejal Kudav <tkudav@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2551897 Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
78 lines
2.7 KiB
C
78 lines
2.7 KiB
C
/*
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* GK20A Graphics Copy Engine (gr host)
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*
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* Copyright (c) 2011-2021, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/kmem.h>
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#include <nvgpu/dma.h>
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#include <nvgpu/log.h>
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#include <nvgpu/enabled.h>
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#include <nvgpu/io.h>
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#include <nvgpu/utils.h>
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#include <nvgpu/gk20a.h>
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#include <nvgpu/cic_mon.h>
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#include <nvgpu/mc.h>
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#include <nvgpu/channel.h>
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#include <nvgpu/engines.h>
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#include "ce2_gk20a.h"
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#include <nvgpu/hw/gk20a/hw_ce2_gk20a.h>
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void gk20a_ce2_stall_isr(struct gk20a *g, u32 inst_id, u32 pri_base)
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{
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u32 ce2_intr = nvgpu_readl(g, ce2_intr_status_r());
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u32 clear_intr = 0U;
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nvgpu_log(g, gpu_dbg_intr, "ce2 isr %08x", ce2_intr);
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/* clear blocking interrupts: they exibit broken behavior */
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if ((ce2_intr & ce2_intr_status_blockpipe_pending_f()) != 0U) {
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nvgpu_log(g, gpu_dbg_intr, "ce2 blocking pipe interrupt");
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clear_intr |= ce2_intr_status_blockpipe_pending_f();
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}
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if ((ce2_intr & ce2_intr_status_launcherr_pending_f()) != 0U) {
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nvgpu_log(g, gpu_dbg_intr, "ce2 launch error interrupt");
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clear_intr |= ce2_intr_status_launcherr_pending_f();
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}
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nvgpu_writel(g, ce2_intr_status_r(), clear_intr);
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}
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u32 gk20a_ce2_nonstall_isr(struct gk20a *g, u32 inst_id, u32 pri_base)
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{
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u32 ops = 0U;
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u32 ce2_intr = nvgpu_readl(g, ce2_intr_status_r());
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nvgpu_log(g, gpu_dbg_intr, "ce2 nonstall isr %08x", ce2_intr);
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if ((ce2_intr & ce2_intr_status_nonblockpipe_pending_f()) != 0U) {
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nvgpu_log(g, gpu_dbg_intr, "ce2 non-blocking pipe interrupt");
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nvgpu_writel(g, ce2_intr_status_r(),
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ce2_intr_status_nonblockpipe_pending_f());
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ops |= (NVGPU_CIC_NONSTALL_OPS_WAKEUP_SEMAPHORE |
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NVGPU_CIC_NONSTALL_OPS_POST_EVENTS);
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}
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return ops;
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}
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