nv-tegra-mirror/linux-nvgpu
1
0
Fork 0
mirror of git://nv-tegra.nvidia.com/linux-nvgpu.git synced 2025-12-24 10:34:43 +03:00
Code Issues Packages Projects Releases Wiki Activity

gpu: nvgpu: Create CIC-mon and CIC-rm subunits

Browse Source 
common.cic unit is divided into common.cic.mon and common.cic.rm
based on rm and mon process split.

CIC-mon subunit includes the code which is utilized in critical
interrupt handling path like initialization, error detection and
error reporting path. CIC-rm subunit includes the code corresponding
to rest of interrupt handling(like collecting error debug data from
registers) and ISR status management (status of deferred interrupts).

Split the CIC APIs and data-members into above two subunits.

JIRA NVGPU-6899

Change-Id: I151b59105ff570607c4a62e974785e9c1323ef69
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2551897
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
tkudav
2021-06-30 15:45:08 +05:30
committed by mobile promotions
parent 8ccf9820ba
commit 0526e7eaa9
82 changed files with 934 additions and 733 deletions
Download Patch File Download Diff File Expand all files Collapse all files

9
userspace/units/acr/nvgpu-acr.c
View File

@@ -35,7 +35,7 @@
#include <nvgpu/firmware.h>
#include <nvgpu/netlist.h>
#include <nvgpu/fuse.h>
#include <nvgpu/cic.h>
#include <nvgpu/cic_mon.h>
#include <nvgpu/gr/gr.h>
@@ -219,11 +219,16 @@ static int init_acr_falcon_test_env(struct unit_module *m, struct gk20a *g)
return -ENODEV;
}
err = nvgpu_cic_init_common(g);
err = nvgpu_cic_mon_setup(g);
if (err != 0) {
unit_return_fail(m, "CIC init failed\n");
}
err = nvgpu_cic_mon_init_lut(g);
if (err != 0) {
unit_return_fail(m, "CIC LUT init failed\n");
}
/*
* Register space: FB_MMU
*/

16
userspace/units/bus/nvgpu-bus.c
View File

@@ -25,7 +25,7 @@
#include <nvgpu/posix/io.h>
#include <unit/core.h>
#include <nvgpu/io.h>
#include <nvgpu/cic.h>
#include <nvgpu/cic_mon.h>
#include <os/posix/os_posix.h>
#include <nvgpu/posix/posix-fault-injection.h>
@@ -36,7 +36,7 @@
#include <hal/bus/bus_gm20b.h>
#include <hal/bus/bus_gp10b.h>
#include <hal/bus/bus_gv11b.h>
#include <hal/cic/cic_gv11b.h>
#include <hal/cic/mon/cic_gv11b.h>
#include <nvgpu/hw/gv11b/hw_mc_gv11b.h>
#include <nvgpu/hw/gv11b/hw_bus_gv11b.h>
@@ -130,8 +130,8 @@ int test_bus_setup(struct unit_module *m, struct gk20a *g, void *args)
g->ops.mc.intr_nonstall_unit_config =
mc_gp10b_intr_nonstall_unit_config;
g->ops.ptimer.isr = gk20a_ptimer_isr;
g->ops.cic.init = gv11b_cic_init;
g->ops.cic.report_err = nvgpu_cic_report_err_safety_services;
g->ops.cic_mon.init = gv11b_cic_mon_init;
g->ops.cic_mon.report_err = nvgpu_cic_mon_report_err_safety_services;
/* Map register space NV_PRIV_MASTER */
if (nvgpu_posix_io_add_reg_space(g, NV_PBUS_START, NV_PBUS_SIZE) != 0) {
@@ -158,12 +158,18 @@ int test_bus_setup(struct unit_module *m, struct gk20a *g, void *args)
(void)nvgpu_posix_register_io(g, &test_reg_callbacks);
if (nvgpu_cic_init_common(g) != 0) {
if (nvgpu_cic_mon_setup(g) != 0) {
unit_err(m, "%s: Failed to initialize CIC\n",
__func__);
return UNIT_FAIL;
}
if (nvgpu_cic_mon_init_lut(g) != 0) {
unit_err(m, "%s: Failed to initialize CIC LUT\n",
__func__);
return UNIT_FAIL;
}
return UNIT_SUCCESS;
}

16
userspace/units/ce/nvgpu-ce.c
View File

@@ -27,10 +27,10 @@
#include <nvgpu/gk20a.h>
#include <nvgpu/device.h>
#include <nvgpu/ce.h>
#include <nvgpu/cic.h>
#include <nvgpu/cic_mon.h>
#include <hal/ce/ce_gp10b.h>
#include <hal/ce/ce_gv11b.h>
#include <hal/cic/cic_gv11b.h>
#include <hal/cic/mon/cic_gv11b.h>
#include <nvgpu/hw/gv11b/hw_ce_gv11b.h>
#include "nvgpu-ce.h"
@@ -128,15 +128,21 @@ int test_ce_setup_env(struct unit_module *m,
g->blcg_enabled = false;
nvgpu_spinlock_init(&g->mc.intr_lock);
g->ops.cic.init = gv11b_cic_init;
g->ops.cic.report_err = nvgpu_cic_report_err_safety_services;
g->ops.cic_mon.init = gv11b_cic_mon_init;
g->ops.cic_mon.report_err = nvgpu_cic_mon_report_err_safety_services;
if (nvgpu_cic_init_common(g) != 0) {
if (nvgpu_cic_mon_setup(g) != 0) {
unit_err(m, "%s: failed to initialize CIC\n",
__func__);
return UNIT_FAIL;
}
if (nvgpu_cic_mon_init_lut(g) != 0) {
unit_err(m, "%s: failed to initialize CIC LUT\n",
__func__);
return UNIT_FAIL;
}
return UNIT_SUCCESS;
}

14
userspace/units/fb/fb_gv11b_fusa.c
View File

@@ -27,7 +27,7 @@
#include <nvgpu/gk20a.h>
#include <nvgpu/io.h>
#include <nvgpu/cic.h>
#include <nvgpu/cic_mon.h>
#include <nvgpu/nvgpu_init.h>
#include "hal/mc/mc_gp10b.h"
#include "hal/fb/fb_gm20b.h"
@@ -35,7 +35,7 @@
#include "hal/fb/ecc/fb_ecc_gv11b.h"
#include "hal/fb/intr/fb_intr_gv11b.h"
#include "hal/fb/intr/fb_intr_ecc_gv11b.h"
#include "hal/cic/cic_gv11b.h"
#include "hal/cic/mon/cic_gv11b.h"
#include <nvgpu/hw/gv11b/hw_fb_gv11b.h>
#include "fb_fusa.h"
@@ -64,8 +64,8 @@ int fb_gv11b_init_test(struct unit_module *m, struct gk20a *g, void *args)
g->ops.mc.intr_nonstall_unit_config =
mc_gp10b_intr_nonstall_unit_config;
g->ops.fb.intr.enable = gv11b_fb_intr_enable;
g->ops.cic.init = gv11b_cic_init;
g->ops.cic.report_err = nvgpu_cic_report_err_safety_services;
g->ops.cic_mon.init = gv11b_cic_mon_init;
g->ops.cic_mon.report_err = nvgpu_cic_mon_report_err_safety_services;
/*
* Define some arbitrary addresses for test purposes.
@@ -78,10 +78,14 @@ int fb_gv11b_init_test(struct unit_module *m, struct gk20a *g, void *args)
g->mm.mmu_rd_mem.cpu_va = (void *) 0x30000000;
g->mm.mmu_rd_mem.aperture = APERTURE_SYSMEM;
if (nvgpu_cic_init_common(g) != 0) {
if (nvgpu_cic_mon_setup(g) != 0) {
unit_return_fail(m, "CIC init failed\n");
}
if (nvgpu_cic_mon_init_lut(g) != 0) {
unit_return_fail(m, "CIC LUT init failed\n");
}
g->ops.ecc.ecc_init_support(g);
nvgpu_writel(g, fb_niso_intr_en_set_r(0), 0);

9
userspace/units/fifo/nvgpu-fifo-common.c
View File

@@ -32,7 +32,7 @@
#include <nvgpu/fifo/userd.h>
#include <nvgpu/gk20a.h>
#include <nvgpu/device.h>
#include <nvgpu/cic.h>
#include <nvgpu/cic_mon.h>
#include <nvgpu/posix/io.h>
@@ -188,12 +188,17 @@ int test_fifo_init_support(struct unit_module *m, struct gk20a *g, void *args)
/* Do not allocate from vidmem */
nvgpu_set_enabled(g, NVGPU_MM_UNIFIED_MEMORY, true);
err = nvgpu_cic_init_common(g);
err = nvgpu_cic_mon_setup(g);
if (err != 0) {
unit_err(m, "CIC init failed!\n");
return UNIT_FAIL;
}
err = nvgpu_cic_mon_init_lut(g);
if (err != 0) {
unit_return_fail(m, "CIC LUT init failed\n");
}
return UNIT_SUCCESS;
fail:

15
userspace/units/gr/nvgpu-gr.c
View File

@@ -33,12 +33,12 @@
#include <nvgpu/netlist.h>
#include <nvgpu/gr/gr.h>
#include <nvgpu/gr/gr_falcon.h>
#include <nvgpu/cic.h>
#include <nvgpu/cic_mon.h>
#include "common/gr/gr_falcon_priv.h"
#include "hal/init/hal_gv11b.h"
#include "hal/cic/cic_gv11b.h"
#include "hal/cic/mon/cic_gv11b.h"
#include "nvgpu-gr.h"
#include "nvgpu-gr-gv11b.h"
@@ -167,14 +167,19 @@ int test_gr_init_setup_ready(struct unit_module *m,
nvgpu_device_init(g);
nvgpu_fifo_setup_sw(g);
g->ops.cic.init = gv11b_cic_init;
g->ops.cic.report_err = nvgpu_cic_report_err_safety_services;
g->ops.cic_mon.init = gv11b_cic_mon_init;
g->ops.cic_mon.report_err = nvgpu_cic_mon_report_err_safety_services;
err = nvgpu_cic_init_common(g);
err = nvgpu_cic_mon_setup(g);
if (err != 0) {
unit_return_fail(m, "CIC init failed\n");
}
err = nvgpu_cic_mon_init_lut(g);
if (err != 0) {
unit_return_fail(m, "CIC LUT init failed\n");
}
/* Allocate and Initialize GR */
err = test_gr_init_setup(m, g, args);
if (err != 0) {

9
userspace/units/ltc/nvgpu-ltc.c
View File

@@ -37,7 +37,7 @@
#include <nvgpu/nvgpu_mem.h>
#include <nvgpu/ecc.h>
#include <nvgpu/netlist.h>
#include <nvgpu/cic.h>
#include <nvgpu/cic_mon.h>
#include <nvgpu/gr/gr.h>
#include <hal/ltc/intr/ltc_intr_gv11b.h>
#include <nvgpu/vm.h>
@@ -137,11 +137,16 @@ int test_ltc_init_support(struct unit_module *m,
unit_return_fail(m, "nvgpu_init_hal failed\n");
}
err = nvgpu_cic_init_common(g);
err = nvgpu_cic_mon_setup(g);
if (err != 0) {
unit_return_fail(m, "CIC init failed\n");
}
err = nvgpu_cic_mon_init_lut(g);
if (err != 0) {
unit_return_fail(m, "CIC LUT init failed\n");
}
/*
* Init dependent ECC unit
*/

37
userspace/units/mc/nvgpu-mc.c
View File

@@ -26,7 +26,8 @@
#include <nvgpu/gk20a.h>
#include <nvgpu/mc.h>
#include <nvgpu/cic.h>
#include <nvgpu/cic_mon.h>
#include <nvgpu/cic_rm.h>
#include <nvgpu/hal_init.h>
#include <nvgpu/device.h>
#include <nvgpu/engines.h>
@@ -284,7 +285,7 @@ int test_unit_config(struct unit_module *m, struct gk20a *g, void *args)
unit = mc_units[i].num;
/* enable stall intr */
nvgpu_cic_intr_stall_unit_config(g, unit, true);
nvgpu_cic_mon_intr_stall_unit_config(g, unit, true);
val = nvgpu_posix_io_readl_reg_space(g, STALL_EN_REG);
if (val != mc_units[i].bit) {
unit_return_fail(m, "failed to enable stall intr for unit %u val=0x%08x\n",
@@ -292,7 +293,7 @@ int test_unit_config(struct unit_module *m, struct gk20a *g, void *args)
}
/* disable stall intr */
nvgpu_cic_intr_stall_unit_config(g, unit, false);
nvgpu_cic_mon_intr_stall_unit_config(g, unit, false);
val = nvgpu_posix_io_readl_reg_space(g, STALL_DIS_REG);
if (val != mc_units[i].bit) {
unit_return_fail(m, "failed to disable stall intr for unit %u val=0x%08x\n",
@@ -300,7 +301,7 @@ int test_unit_config(struct unit_module *m, struct gk20a *g, void *args)
}
/* enable nonstall intr */
nvgpu_cic_intr_nonstall_unit_config(g, unit, true);
nvgpu_cic_mon_intr_nonstall_unit_config(g, unit, true);
val = nvgpu_posix_io_readl_reg_space(g, NONSTALL_EN_REG);
if (val != mc_units[i].bit) {
unit_return_fail(m, "failed to enable nonstall intr for unit %u val=0x%08x\n",
@@ -308,7 +309,7 @@ int test_unit_config(struct unit_module *m, struct gk20a *g, void *args)
}
/* disable stall intr */
nvgpu_cic_intr_nonstall_unit_config(g, unit, false);
nvgpu_cic_mon_intr_nonstall_unit_config(g, unit, false);
val = nvgpu_posix_io_readl_reg_space(g, NONSTALL_DIS_REG);
if (val != mc_units[i].bit) {
unit_return_fail(m, "failed to disable nonstall intr for unit %u val=0x%08x\n",
@@ -318,7 +319,7 @@ int test_unit_config(struct unit_module *m, struct gk20a *g, void *args)
/* negative testing - invalid unit - stall */
nvgpu_posix_io_writel_reg_space(g, STALL_EN_REG, 0x0); /* clear reg */
nvgpu_cic_intr_stall_unit_config(g, U32_MAX, true);
nvgpu_cic_mon_intr_stall_unit_config(g, U32_MAX, true);
val = nvgpu_posix_io_readl_reg_space(g, STALL_EN_REG);
if (val != 0U) {
unit_return_fail(m, "Incorrectly enabled interrupt for invalid unit, val=0x%08x\n",
@@ -327,7 +328,7 @@ int test_unit_config(struct unit_module *m, struct gk20a *g, void *args)
/* negative testing - invalid unit - nonstall */
nvgpu_posix_io_writel_reg_space(g, NONSTALL_EN_REG, 0x0); /* clear reg */
nvgpu_cic_intr_nonstall_unit_config(g, U32_MAX, true);
nvgpu_cic_mon_intr_nonstall_unit_config(g, U32_MAX, true);
val = nvgpu_posix_io_readl_reg_space(g, NONSTALL_EN_REG);
if (val != 0U) {
unit_return_fail(m, "Incorrectly enabled interrupt for invalid unit, val=0x%08x\n",
@@ -355,18 +356,18 @@ int test_pause_resume_mask(struct unit_module *m, struct gk20a *g, void *args)
g->mc.intr_mask_restore[1] = 0U;
/* enable something to pause and resume */
nvgpu_cic_intr_stall_unit_config(g, NVGPU_CIC_INTR_UNIT_PRIV_RING, true);
nvgpu_cic_intr_nonstall_unit_config(g, NVGPU_CIC_INTR_UNIT_BUS, true);
nvgpu_cic_mon_intr_stall_unit_config(g, NVGPU_CIC_INTR_UNIT_PRIV_RING, true);
nvgpu_cic_mon_intr_nonstall_unit_config(g, NVGPU_CIC_INTR_UNIT_BUS, true);
/* pause stall */
nvgpu_cic_intr_stall_pause(g);
nvgpu_cic_mon_intr_stall_pause(g);
val = nvgpu_posix_io_readl_reg_space(g, STALL_DIS_REG);
if (val != U32_MAX) {
unit_return_fail(m, "failed to pause stall intr\n");
}
/* pause nonstall */
nvgpu_cic_intr_nonstall_pause(g);
nvgpu_cic_mon_intr_nonstall_pause(g);
val = nvgpu_posix_io_readl_reg_space(g, NONSTALL_DIS_REG);
if (val != U32_MAX) {
unit_return_fail(m, "failed to pause nonstall intr\n");
@@ -374,7 +375,7 @@ int test_pause_resume_mask(struct unit_module *m, struct gk20a *g, void *args)
/* resume stall */
nvgpu_posix_io_writel_reg_space(g, STALL_EN_REG, 0x0);
nvgpu_cic_intr_stall_resume(g);
nvgpu_cic_mon_intr_stall_resume(g);
val = nvgpu_posix_io_readl_reg_space(g, STALL_EN_REG);
if (val != expected_stall_val) {
unit_return_fail(m, "failed to resume stall intr\n");
@@ -382,7 +383,7 @@ int test_pause_resume_mask(struct unit_module *m, struct gk20a *g, void *args)
/* resume nonstall */
nvgpu_posix_io_writel_reg_space(g, NONSTALL_EN_REG, 0x0);
nvgpu_cic_intr_nonstall_resume(g);
nvgpu_cic_mon_intr_nonstall_resume(g);
val = nvgpu_posix_io_readl_reg_space(g, NONSTALL_EN_REG);
if (val != expected_nonstall_val) {
unit_return_fail(m, "failed to resume nonstall intr\n");
@@ -393,7 +394,7 @@ int test_pause_resume_mask(struct unit_module *m, struct gk20a *g, void *args)
nvgpu_posix_io_writel_reg_space(g, NONSTALL_DIS_REG, 0x0);
/* mask all */
nvgpu_cic_intr_mask(g);
nvgpu_cic_mon_intr_mask(g);
val = nvgpu_posix_io_readl_reg_space(g, STALL_DIS_REG);
if (val != U32_MAX) {
unit_return_fail(m, "failed to mask stall intr\n");
@@ -406,7 +407,7 @@ int test_pause_resume_mask(struct unit_module *m, struct gk20a *g, void *args)
/* make this HAL NULL for branch coverage */
save_func = g->ops.mc.intr_mask;
g->ops.mc.intr_mask = NULL;
nvgpu_cic_intr_mask(g);
nvgpu_cic_mon_intr_mask(g);
g->ops.mc.intr_mask = save_func;
return UNIT_SUCCESS;
@@ -664,18 +665,18 @@ int test_wait_for_deferred_interrupts(struct unit_module *m, struct gk20a *g,
/* immediate completion */
nvgpu_atomic_set(&g->mc.sw_irq_stall_pending, 0);
nvgpu_atomic_set(&g->mc.sw_irq_nonstall_pending, 0);
nvgpu_cic_wait_for_deferred_interrupts(g);
nvgpu_cic_rm_wait_for_deferred_interrupts(g);
/* cause timeout */
nvgpu_posix_enable_fault_injection(cond_fi, true, 0);
/* wait on stall until timeout for branch coverage */
nvgpu_atomic_set(&g->mc.sw_irq_stall_pending, 1);
nvgpu_cic_wait_for_deferred_interrupts(g);
nvgpu_cic_rm_wait_for_deferred_interrupts(g);
/* wait on nonstall until timeout for branch coverage */
nvgpu_atomic_set(&g->mc.sw_irq_nonstall_pending, 1);
nvgpu_cic_wait_for_deferred_interrupts(g);
nvgpu_cic_rm_wait_for_deferred_interrupts(g);
/* disable the fault injection */
nvgpu_posix_enable_fault_injection(cond_fi, false, 0);

24
userspace/units/mc/nvgpu-mc.h
View File

@@ -74,12 +74,12 @@ int test_mc_free_env(struct unit_module *m, struct gk20a *g, void *args);
/**
* Test specification for: test_unit_config
*
* Description: Validate function of nvgpu_cic_intr_stall_unit_config and
* nvgpu_cic_intr_nonstall_unit_config.
* Description: Validate function of nvgpu_cic_mon_intr_stall_unit_config and
* nvgpu_cic_mon_intr_nonstall_unit_config.
*
* Test Type: Feature, Error guessing
*
* Targets: nvgpu_cic_intr_stall_unit_config, nvgpu_cic_intr_nonstall_unit_config,
* Targets: nvgpu_cic_mon_intr_stall_unit_config, nvgpu_cic_mon_intr_nonstall_unit_config,
* mc_gp10b_intr_stall_unit_config, mc_gp10b_intr_nonstall_unit_config
*
* Input: test_mc_setup_env must have been run.
@@ -88,22 +88,22 @@ int test_mc_free_env(struct unit_module *m, struct gk20a *g, void *args);
* - Set each of the mock registers for enabling & disabling the stall &
* non-stall interrupts to 0.
* - Loop through table of units:
* - Call nvgpu_cic_intr_stall_unit_config for the unit to enable the stall
* - Call nvgpu_cic_mon_intr_stall_unit_config for the unit to enable the stall
* interrupt.
* - Verify the stall interrupt enable register has the bit set for the unit.
* - Call nvgpu_cic_intr_stall_unit_config for the unit to disable the interrupt.
* - Call nvgpu_cic_mon_intr_stall_unit_config for the unit to disable the interrupt.
* - Verify the stall interrupt disable register has the bit set for the unit.
* - Call nvgpu_cic_intr_nonstall_unit_config for the unit to enable the
* - Call nvgpu_cic_mon_intr_nonstall_unit_config for the unit to enable the
* non-stall interrupt.
* - Verify the non-stall interrupt enable register has the bit set for the unit.
* - Call nvgpu_cic_intr_nonstall_unit_config for the unit to disable the interrupt.
* - Call nvgpu_cic_mon_intr_nonstall_unit_config for the unit to disable the interrupt.
* - Verify the non-stall interrupt disable register has the bit set for the unit.
* - Clear the stall enable register.
* - For negative testing, call nvgpu_cic_intr_stall_unit_config() with an
* - For negative testing, call nvgpu_cic_mon_intr_stall_unit_config() with an
* invalid unit number, and verify no bits are set in the stall interrupt
* enable register.
* - Clear the stall enable register.
* - For negative testing, call nvgpu_cic_intr_nonstall_unit_config() with an
* - For negative testing, call nvgpu_cic_mon_intr_nonstall_unit_config() with an
* invalid unit number, and verify no bits are set in the non-stall interrupt
* enable register.
*
@@ -118,9 +118,9 @@ int test_unit_config(struct unit_module *m, struct gk20a *g, void *args);
*
* Test Type: Feature
*
* Targets: nvgpu_cic_intr_stall_pause, nvgpu_cic_intr_stall_resume,
* nvgpu_cic_intr_nonstall_pause, nvgpu_cic_intr_nonstall_resume,
* nvgpu_cic_intr_mask, mc_gp10b_intr_stall_pause,
* Targets: nvgpu_cic_mon_intr_stall_pause, nvgpu_cic_mon_intr_stall_resume,
* nvgpu_cic_mon_intr_nonstall_pause, nvgpu_cic_mon_intr_nonstall_resume,
* nvgpu_cic_mon_intr_mask, mc_gp10b_intr_stall_pause,
* mc_gp10b_intr_stall_resume, mc_gp10b_intr_nonstall_pause,
* mc_gp10b_intr_nonstall_resume, mc_gp10b_intr_mask
*

14
userspace/units/mm/hal/mmu_fault/gv11b_fusa/mmu-fault-gv11b-fusa.c
View File

@@ -37,7 +37,7 @@
#include <nvgpu/tsg.h>
#include <nvgpu/engines.h>
#include <nvgpu/preempt.h>
#include <nvgpu/cic.h>
#include <nvgpu/cic_mon.h>
#include <nvgpu/nvgpu_init.h>
#include <nvgpu/hw/gv11b/hw_fb_gv11b.h>
#include <nvgpu/hw/gv11b/hw_gmmu_gv11b.h>
@@ -61,7 +61,7 @@
#include "hal/mm/gmmu/gmmu_gv11b.h"
#include "hal/mm/mm_gp10b.h"
#include "hal/mm/mm_gv11b.h"
#include "hal/cic/cic_gv11b.h"
#include "hal/cic/mon/cic_gv11b.h"
#include "hal/mm/mmu_fault/mmu_fault_gv11b.h"
#include "mmu-fault-gv11b-fusa.h"
@@ -222,13 +222,17 @@ int test_env_init_mm_mmu_fault_gv11b_fusa(struct unit_module *m,
unit_return_fail(m, "nvgpu_init_mm_support failed\n");
}
g->ops.cic.init = gv11b_cic_init;
g->ops.cic.report_err = nvgpu_cic_report_err_safety_services;
g->ops.cic_mon.init = gv11b_cic_mon_init;
g->ops.cic_mon.report_err = nvgpu_cic_mon_report_err_safety_services;
if (nvgpu_cic_init_common(g) != 0) {
if (nvgpu_cic_mon_setup(g) != 0) {
unit_return_fail(m, "Failed to initialize CIC\n");
}
if (nvgpu_cic_mon_init_lut(g) != 0) {
unit_return_fail(m, "Failed to initialize CIC LUT\n");
}
return UNIT_SUCCESS;
}

16
userspace/units/priv_ring/nvgpu-priv_ring.c
View File

@@ -23,14 +23,14 @@
#include <unit/unit.h>
#include <unit/io.h>
#include <nvgpu/posix/io.h>
#include <nvgpu/cic.h>
#include <nvgpu/cic_mon.h>
#include <nvgpu/gk20a.h>
#include <hal/priv_ring/priv_ring_gm20b.h>
#include <hal/priv_ring/priv_ring_gp10b.h>
#include <hal/init/hal_gv11b_litter.h>
#include <hal/mc/mc_gp10b.h>
#include "hal/cic/cic_gv11b.h"
#include "hal/cic/mon/cic_gv11b.h"
#include <nvgpu/hw/gv11b/hw_pri_ringstation_sys_gv11b.h>
#include <nvgpu/hw/gv11b/hw_pri_ringstation_gpc_gv11b.h>
@@ -125,8 +125,8 @@ int test_priv_ring_setup(struct unit_module *m, struct gk20a *g, void *args)
g->ops.get_litter_value = gv11b_get_litter_value;
g->ops.mc.intr_stall_unit_config =
mc_gp10b_intr_stall_unit_config;
g->ops.cic.init = gv11b_cic_init;
g->ops.cic.report_err = nvgpu_cic_report_err_safety_services;
g->ops.cic_mon.init = gv11b_cic_mon_init;
g->ops.cic_mon.report_err = nvgpu_cic_mon_report_err_safety_services;
/* Map register space NV_PRIV_MASTER */
if (nvgpu_posix_io_add_reg_space(g, NV_PRIV_MASTER_START,
@@ -162,12 +162,18 @@ int test_priv_ring_setup(struct unit_module *m, struct gk20a *g, void *args)
(void)nvgpu_posix_register_io(g, &test_reg_callbacks);
if (nvgpu_cic_init_common(g) != 0) {
if (nvgpu_cic_mon_setup(g) != 0) {
unit_err(m, "%s: Failed to initialize CIC\n",
__func__);
return UNIT_FAIL;
}
if (nvgpu_cic_mon_init_lut(g) != 0) {
unit_err(m, "%s: Failed to initialize CIC LUT\n",
__func__);
return UNIT_FAIL;
}
return UNIT_SUCCESS;
}

16
userspace/units/ptimer/nvgpu-ptimer.c
View File

@@ -26,9 +26,9 @@
#include <nvgpu/gk20a.h>
#include <nvgpu/ptimer.h>
#include <nvgpu/cic.h>
#include <nvgpu/cic_mon.h>
#include <hal/ptimer/ptimer_gk20a.h>
#include <hal/cic/cic_gv11b.h>
#include <hal/cic/mon/cic_gv11b.h>
#include <nvgpu/hw/gk20a/hw_timer_gk20a.h>
#include "nvgpu-ptimer.h"
@@ -90,8 +90,8 @@ int test_setup_env(struct unit_module *m,
g->ops.ptimer.read_ptimer = gk20a_read_ptimer;
g->ops.ptimer.isr = gk20a_ptimer_isr;
g->ops.cic.init = gv11b_cic_init;
g->ops.cic.report_err = nvgpu_cic_report_err_safety_services;
g->ops.cic_mon.init = gv11b_cic_mon_init;
g->ops.cic_mon.report_err = nvgpu_cic_mon_report_err_safety_services;
/* Create ptimer register space */
if (nvgpu_posix_io_add_reg_space(g, PTIMER_REG_SPACE_START,
@@ -102,12 +102,18 @@ int test_setup_env(struct unit_module *m,
}
(void)nvgpu_posix_register_io(g, &test_reg_callbacks);
if (nvgpu_cic_init_common(g) != 0) {
if (nvgpu_cic_mon_setup(g) != 0) {
unit_err(m, "%s: failed to initialize CIC\n",
__func__);
return UNIT_FAIL;
}
if (nvgpu_cic_mon_init_lut(g) != 0) {
unit_err(m, "%s: failed to initialize CIC LUT\n",
__func__);
return UNIT_FAIL;
}
return UNIT_SUCCESS;
}