nv-tegra-mirror/linux-nvgpu
1
0
Fork 0
mirror of git://nv-tegra.nvidia.com/linux-nvgpu.git synced 2025-12-22 17:36:20 +03:00
Code Issues Packages Projects Releases Wiki Activity

gpu: nvgpu: MISRA 10.3 Conversions to/from char

Browse Source 
MISRA Rule 10.3 states that the value of an expression shall not be
assigned to an object with a narrower essential type or of a
different essential type category.

We have cases where we are converting to/from char and non char types
and this fix 10.3 violations resulting from these conversions.

This also fix violations in conversions between s8 and non-s8 types
as s8 can be typedefed as char.

Jira NVGPU-1010

Change-Id: I150dd633eb7575de9ea2bedd598b7af74d1fcbd9
Signed-off-by: Sai Nikhil <snikhil@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1801613
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Adeel Raza <araza@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Sai Nikhil
2018-08-21 12:18:10 +05:30
committed by mobile promotions
parent 9f5a464d28
commit 05f45bcfc3
4 changed files with 20 additions and 16 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
drivers/gpu/nvgpu/clk/clk_vin.c
View File

@@ -102,8 +102,8 @@ u32 clk_avfs_get_vin_cal_fuse_v20(struct gk20a *g,
if (pvinobjs->calibration_rev_vbios == g->ops.fuse.read_vin_cal_fuse_rev(g)) {
BOARDOBJGRP_FOR_EACH(&(pvinobjs->super.super),
struct vin_device_v20 *, pvindev, i) {
gain = 0;
offset = 0;
gain = '\0';
offset = '\0';
pvindev = (struct vin_device_v20 *)CLK_GET_VIN_DEVICE(pvinobjs, i);
status = g->ops.fuse.read_vin_cal_gain_offset_fuse(g,
pvindev->super.id, &gain, &offset);
@@ -268,7 +268,7 @@ static u32 devinit_get_vin_device_table(struct gk20a *g,
u8 *vin_tbl_entry_ptr = NULL;
u32 index = 0;
u32 slope=0, intercept=0;
s8 offset=0, gain=0;
s8 offset='\0', gain='\0';
struct vin_device *pvin_dev;
u32 cal_type;

26
drivers/gpu/nvgpu/common/fuse/fuse_gp106.c
View File

@@ -181,50 +181,54 @@ u32 gp106_fuse_read_vin_cal_gain_offset_fuse(struct gk20a *g,
u32 vin_id, s8 *gain,
s8 *offset)
{
u32 reg_val = 0;
u32 data = 0;
switch (vin_id) {
case CTRL_CLK_VIN_ID_GPC0:
data = gk20a_readl(g, fuse_vin_cal_gpc0_r());
reg_val = gk20a_readl(g, fuse_vin_cal_gpc0_r());
break;
case CTRL_CLK_VIN_ID_GPC1:
data = gk20a_readl(g, fuse_vin_cal_gpc1_delta_r());
reg_val = gk20a_readl(g, fuse_vin_cal_gpc1_delta_r());
break;
case CTRL_CLK_VIN_ID_GPC2:
data = gk20a_readl(g, fuse_vin_cal_gpc2_delta_r());
reg_val = gk20a_readl(g, fuse_vin_cal_gpc2_delta_r());
break;
case CTRL_CLK_VIN_ID_GPC3:
data = gk20a_readl(g, fuse_vin_cal_gpc3_delta_r());
reg_val = gk20a_readl(g, fuse_vin_cal_gpc3_delta_r());
break;
case CTRL_CLK_VIN_ID_GPC4:
data = gk20a_readl(g, fuse_vin_cal_gpc4_delta_r());
reg_val = gk20a_readl(g, fuse_vin_cal_gpc4_delta_r());
break;
case CTRL_CLK_VIN_ID_GPC5:
data = gk20a_readl(g, fuse_vin_cal_gpc5_delta_r());
reg_val = gk20a_readl(g, fuse_vin_cal_gpc5_delta_r());
break;
case CTRL_CLK_VIN_ID_SYS:
case CTRL_CLK_VIN_ID_XBAR:
case CTRL_CLK_VIN_ID_LTC:
data = gk20a_readl(g, fuse_vin_cal_shared_delta_r());
reg_val = gk20a_readl(g, fuse_vin_cal_shared_delta_r());
break;
case CTRL_CLK_VIN_ID_SRAM:
data = gk20a_readl(g, fuse_vin_cal_sram_delta_r());
reg_val = gk20a_readl(g, fuse_vin_cal_sram_delta_r());
break;
default:
return -EINVAL;
}
if (data == 0xFFFFFFFF)
if (reg_val == 0xFFFFFFFF) {
return -EINVAL;
*gain = (s8) (data >> 16) & 0x1f;
*offset = (s8) data & 0x7f;
}
data = (reg_val >> 16U) & 0x1fU;
*gain = (s8)data;
data = reg_val & 0x7fU;
*offset = (s8)data;
return 0;
}

2
drivers/gpu/nvgpu/common/mm/nvgpu_allocator.c
View File

@@ -169,7 +169,7 @@ int __nvgpu_alloc_common_init(struct nvgpu_allocator *a, struct gk20a *g,
a->debug = dbg;
strncpy(a->name, name, sizeof(a->name));
a->name[sizeof(a->name) - 1] = 0;
a->name[sizeof(a->name) - 1U] = '\0';
return 0;
}

2
drivers/gpu/nvgpu/gk20a/pmu_gk20a.c
View File

@@ -96,7 +96,7 @@ static void print_pmu_trace(struct nvgpu_pmu *pmu)
if (k >= 40)
break;
strncpy(part_str, (trace+i+20+m), k);
part_str[k] = 0;
part_str[k] = '\0';
count += scnprintf((buf + count), 0x40, "%s0x%x",
part_str, trace1[(i / 4) + 1 + l]);
l++;