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gpu: nvgpu: netlist: compile out non safety function for safety build

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Move functions used only by sim under CONFIG_NVGPU_NON_FUSA.
Following functions are compiled out for safety build:

void nvgpu_netlist_set_fecs_inst_count(struct gk20a *g, u32 count);
void nvgpu_netlist_set_fecs_data_count(struct gk20a *g, u32 count);
void nvgpu_netlist_set_gpccs_inst_count(struct gk20a *g, u32 count);
void nvgpu_netlist_set_gpccs_data_count(struct gk20a *g, u32 count);

struct netlist_u32_list *nvgpu_netlist_get_fecs_inst(struct gk20a *g);
struct netlist_u32_list *nvgpu_netlist_get_fecs_data(struct gk20a *g);
struct netlist_u32_list *nvgpu_netlist_get_gpccs_inst(struct gk20a *g);
struct netlist_u32_list *nvgpu_netlist_get_gpccs_data(struct gk20a *g);

void nvgpu_netlist_vars_set_dynamic(struct gk20a *g, bool set);
void nvgpu_netlist_vars_set_buffer_size(struct gk20a *g, u32 size);
void nvgpu_netlist_vars_set_regs_base_index(struct gk20a *g, u32 index);

JIRA NVGPU-2773

Change-Id: I37bdf498d5e152dc0d438644e3996835c1150e78
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2208831
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Seshendra Gadagottu
2019-09-27 18:01:45 -07:00
committed by Alex Waterman
parent 67179c661e
commit 0697d4237b
2 changed files with 55 additions and 48 deletions
Download Patch File Download Diff File Expand all files Collapse all files

83
drivers/gpu/nvgpu/common/netlist/netlist.c
View File

@@ -669,26 +669,6 @@ u32 nvgpu_netlist_get_gpccs_data_count(struct gk20a *g)
return g->netlist_vars->ucode.gpccs.data.count;
}
void nvgpu_netlist_set_fecs_inst_count(struct gk20a *g, u32 count)
{
g->netlist_vars->ucode.fecs.inst.count = count;
}
void nvgpu_netlist_set_fecs_data_count(struct gk20a *g, u32 count)
{
g->netlist_vars->ucode.fecs.data.count = count;
}
void nvgpu_netlist_set_gpccs_inst_count(struct gk20a *g, u32 count)
{
g->netlist_vars->ucode.gpccs.inst.count = count;
}
void nvgpu_netlist_set_gpccs_data_count(struct gk20a *g, u32 count)
{
g->netlist_vars->ucode.gpccs.data.count = count;
}
u32 *nvgpu_netlist_get_fecs_inst_list(struct gk20a *g)
{
return g->netlist_vars->ucode.fecs.inst.l;
@@ -709,26 +689,6 @@ u32 *nvgpu_netlist_get_gpccs_data_list(struct gk20a *g)
return g->netlist_vars->ucode.gpccs.data.l;
}
struct netlist_u32_list *nvgpu_netlist_get_fecs_inst(struct gk20a *g)
{
return &g->netlist_vars->ucode.fecs.inst;
}
struct netlist_u32_list *nvgpu_netlist_get_fecs_data(struct gk20a *g)
{
return &g->netlist_vars->ucode.fecs.data;
}
struct netlist_u32_list *nvgpu_netlist_get_gpccs_inst(struct gk20a *g)
{
return &g->netlist_vars->ucode.gpccs.inst;
}
struct netlist_u32_list *nvgpu_netlist_get_gpccs_data(struct gk20a *g)
{
return &g->netlist_vars->ucode.gpccs.data;
}
#ifdef CONFIG_NVGPU_DEBUGGER
struct netlist_aiv_list *nvgpu_netlist_get_sys_ctxsw_regs(struct gk20a *g)
{
@@ -846,6 +806,48 @@ struct netlist_aiv_list *nvgpu_netlist_get_pm_cau_ctxsw_regs(struct gk20a *g)
}
#endif /* CONFIG_NVGPU_DEBUGGER */
#ifdef CONFIG_NVGPU_NON_FUSA
void nvgpu_netlist_set_fecs_inst_count(struct gk20a *g, u32 count)
{
g->netlist_vars->ucode.fecs.inst.count = count;
}
void nvgpu_netlist_set_fecs_data_count(struct gk20a *g, u32 count)
{
g->netlist_vars->ucode.fecs.data.count = count;
}
void nvgpu_netlist_set_gpccs_inst_count(struct gk20a *g, u32 count)
{
g->netlist_vars->ucode.gpccs.inst.count = count;
}
void nvgpu_netlist_set_gpccs_data_count(struct gk20a *g, u32 count)
{
g->netlist_vars->ucode.gpccs.data.count = count;
}
struct netlist_u32_list *nvgpu_netlist_get_fecs_inst(struct gk20a *g)
{
return &g->netlist_vars->ucode.fecs.inst;
}
struct netlist_u32_list *nvgpu_netlist_get_fecs_data(struct gk20a *g)
{
return &g->netlist_vars->ucode.fecs.data;
}
struct netlist_u32_list *nvgpu_netlist_get_gpccs_inst(struct gk20a *g)
{
return &g->netlist_vars->ucode.gpccs.inst;
}
struct netlist_u32_list *nvgpu_netlist_get_gpccs_data(struct gk20a *g)
{
return &g->netlist_vars->ucode.gpccs.data;
}
void nvgpu_netlist_vars_set_dynamic(struct gk20a *g, bool set)
{
g->netlist_vars->dynamic = set;
@@ -860,3 +862,4 @@ void nvgpu_netlist_vars_set_regs_base_index(struct gk20a *g, u32 index)
{
g->netlist_vars->regs_base_index = index;
}
#endif

20
drivers/gpu/nvgpu/include/nvgpu/netlist.h
View File

@@ -88,18 +88,10 @@ u32 nvgpu_netlist_get_fecs_inst_count(struct gk20a *g);
u32 nvgpu_netlist_get_fecs_data_count(struct gk20a *g);
u32 nvgpu_netlist_get_gpccs_inst_count(struct gk20a *g);
u32 nvgpu_netlist_get_gpccs_data_count(struct gk20a *g);
void nvgpu_netlist_set_fecs_inst_count(struct gk20a *g, u32 count);
void nvgpu_netlist_set_fecs_data_count(struct gk20a *g, u32 count);
void nvgpu_netlist_set_gpccs_inst_count(struct gk20a *g, u32 count);
void nvgpu_netlist_set_gpccs_data_count(struct gk20a *g, u32 count);
u32 *nvgpu_netlist_get_fecs_inst_list(struct gk20a *g);
u32 *nvgpu_netlist_get_fecs_data_list(struct gk20a *g);
u32 *nvgpu_netlist_get_gpccs_inst_list(struct gk20a *g);
u32 *nvgpu_netlist_get_gpccs_data_list(struct gk20a *g);
struct netlist_u32_list *nvgpu_netlist_get_fecs_inst(struct gk20a *g);
struct netlist_u32_list *nvgpu_netlist_get_fecs_data(struct gk20a *g);
struct netlist_u32_list *nvgpu_netlist_get_gpccs_inst(struct gk20a *g);
struct netlist_u32_list *nvgpu_netlist_get_gpccs_data(struct gk20a *g);
#ifdef CONFIG_NVGPU_DEBUGGER
struct netlist_aiv_list *nvgpu_netlist_get_sys_ctxsw_regs(struct gk20a *g);
@@ -132,8 +124,20 @@ struct netlist_aiv_list *nvgpu_netlist_get_etpc_ctxsw_regs(struct gk20a *g);
struct netlist_aiv_list *nvgpu_netlist_get_pm_cau_ctxsw_regs(struct gk20a *g);
#endif /* CONFIG_NVGPU_DEBUGGER */
#ifdef CONFIG_NVGPU_NON_FUSA
void nvgpu_netlist_set_fecs_inst_count(struct gk20a *g, u32 count);
void nvgpu_netlist_set_fecs_data_count(struct gk20a *g, u32 count);
void nvgpu_netlist_set_gpccs_inst_count(struct gk20a *g, u32 count);
void nvgpu_netlist_set_gpccs_data_count(struct gk20a *g, u32 count);
struct netlist_u32_list *nvgpu_netlist_get_fecs_inst(struct gk20a *g);
struct netlist_u32_list *nvgpu_netlist_get_fecs_data(struct gk20a *g);
struct netlist_u32_list *nvgpu_netlist_get_gpccs_inst(struct gk20a *g);
struct netlist_u32_list *nvgpu_netlist_get_gpccs_data(struct gk20a *g);
void nvgpu_netlist_vars_set_dynamic(struct gk20a *g, bool set);
void nvgpu_netlist_vars_set_buffer_size(struct gk20a *g, u32 size);
void nvgpu_netlist_vars_set_regs_base_index(struct gk20a *g, u32 index);
#endif
#endif /* NVGPU_NETLIST_H */