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gpu: nvgpu: Remove clk.h dependency from gk20a.h

Browse Source 
gk20a.h depends on definition of struct clk_pmupstate. Change that
to a pointer and use forward declaration, and allocation and free
functions.

Fix a few build breaks by adding explicit includes where previously
a header file had gotten included implicitly.

JIRA NVGPU-596

Change-Id: Iafe7d72a6fd31543653e0e10e2d2e552b6c3514b
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1945286
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Terje Bergstrom
2018-11-07 13:28:12 -08:00
committed by mobile promotions
parent bca27e31e3
commit 07760eb9a1
16 changed files with 124 additions and 87 deletions
Download Patch File Download Diff File Expand all files Collapse all files

36
drivers/gpu/nvgpu/clk/clk.c
View File

@@ -200,7 +200,7 @@ int clk_pmu_freq_controller_load(struct gk20a *g, bool bload, u8 bit_idx)
(void) memset(&rpccall, 0, sizeof(struct nv_pmu_clk_rpc));
(void) memset(&handler, 0, sizeof(struct clkrpc_pmucmdhandler_params));
pclk_freq_controllers = &g->clk_pmu.clk_freq_controllers;
pclk_freq_controllers = &g->clk_pmu->clk_freq_controllers;
rpccall.function = NV_PMU_CLK_RPC_ID_LOAD;
clkload = &rpccall.params.clk_load;
clkload->feature = NV_NV_PMU_CLK_LOAD_FEATURE_FREQ_CONTROLLER;
@@ -500,7 +500,7 @@ static u32 find_regime_id(struct gk20a *g, u32 domain, u16 clkmhz)
{
struct fll_device *pflldev;
u8 j;
struct clk_pmupstate *pclk = &g->clk_pmu;
struct clk_pmupstate *pclk = g->clk_pmu;
BOARDOBJGRP_FOR_EACH(&(pclk->avfs_fllobjs.super.super),
struct fll_device *, pflldev, j) {
@@ -520,7 +520,7 @@ static int set_regime_id(struct gk20a *g, u32 domain, u32 regimeid)
{
struct fll_device *pflldev;
u8 j;
struct clk_pmupstate *pclk = &g->clk_pmu;
struct clk_pmupstate *pclk = g->clk_pmu;
BOARDOBJGRP_FOR_EACH(&(pclk->avfs_fllobjs.super.super),
struct fll_device *, pflldev, j) {
@@ -536,7 +536,7 @@ static int get_regime_id(struct gk20a *g, u32 domain, u32 *regimeid)
{
struct fll_device *pflldev;
u8 j;
struct clk_pmupstate *pclk = &g->clk_pmu;
struct clk_pmupstate *pclk = g->clk_pmu;
BOARDOBJGRP_FOR_EACH(&(pclk->avfs_fllobjs.super.super),
struct fll_device *, pflldev, j) {
@@ -613,7 +613,7 @@ int clk_get_fll_clks(struct gk20a *g, struct set_fll_clk *setfllclk)
int status = -EINVAL;
struct clk_domain *pdomain;
u8 i;
struct clk_pmupstate *pclk = &g->clk_pmu;
struct clk_pmupstate *pclk = g->clk_pmu;
u16 clkmhz = 0;
struct clk_domain_3x_master *p3xmaster;
struct clk_domain_3x_slave *p3xslave;
@@ -674,7 +674,7 @@ int clk_domain_print_vf_table(struct gk20a *g, u32 clkapidomain)
int status = -EINVAL;
struct clk_domain *pdomain;
u8 i;
struct clk_pmupstate *pclk = &g->clk_pmu;
struct clk_pmupstate *pclk = g->clk_pmu;
u16 clkmhz = 0;
u32 volt = 0;
@@ -697,7 +697,7 @@ static int clk_program_fllclks(struct gk20a *g, struct change_fll_clk *fllclk)
int status = -EINVAL;
struct clk_domain *pdomain;
u8 i;
struct clk_pmupstate *pclk = &g->clk_pmu;
struct clk_pmupstate *pclk = g->clk_pmu;
u16 clkmhz = 0;
struct clk_domain_3x_master *p3xmaster;
struct clk_domain_3x_slave *p3xslave;
@@ -916,7 +916,7 @@ int clk_domain_get_f_or_v(
int status = -EINVAL;
struct clk_domain *pdomain;
u8 i;
struct clk_pmupstate *pclk = &g->clk_pmu;
struct clk_pmupstate *pclk = g->clk_pmu;
u8 rail;
if ((pclkmhz == NULL) || (pvoltuv == NULL)) {
@@ -941,3 +941,23 @@ int clk_domain_get_f_or_v(
}
return status;
}
int clk_init_pmupstate(struct gk20a *g)
{
/* If already allocated, do not re-allocate */
if (g->clk_pmu != NULL) {
return 0;
}
g->clk_pmu = nvgpu_kzalloc(g, sizeof(*g->clk_pmu));
if (g->clk_pmu == NULL) {
return -ENOMEM;
}
return 0;
}
void clk_free_pmupstate(struct gk20a *g)
{
nvgpu_kfree(g, g->clk_pmu);
}

2
drivers/gpu/nvgpu/clk/clk.h
View File

@@ -119,6 +119,8 @@ struct vbios_clocks_table_1x_hal_clock_entry {
#define BOOT_GPC2CLK_MHZ 2581U
int clk_init_pmupstate(struct gk20a *g);
void clk_free_pmupstate(struct gk20a *g);
int clk_pmu_vin_load(struct gk20a *g);
int clk_domain_print_vf_table(struct gk20a *g, u32 clkapidomain);
int clk_domain_get_f_or_v(

14
drivers/gpu/nvgpu/clk/clk_domain.c
View File

@@ -198,7 +198,7 @@ int clk_domain_sw_setup(struct gk20a *g)
nvgpu_log_info(g, " ");
status = boardobjgrpconstruct_e32(g, &g->clk_pmu.clk_domainobjs.super);
status = boardobjgrpconstruct_e32(g, &g->clk_pmu->clk_domainobjs.super);
if (status != 0) {
nvgpu_err(g,
"error creating boardobjgrp for clk domain, status - 0x%x",
@@ -206,8 +206,8 @@ int clk_domain_sw_setup(struct gk20a *g)
goto done;
}
pboardobjgrp = &g->clk_pmu.clk_domainobjs.super.super;
pclkdomainobjs = &(g->clk_pmu.clk_domainobjs);
pboardobjgrp = &g->clk_pmu->clk_domainobjs.super.super;
pclkdomainobjs = &(g->clk_pmu->clk_domainobjs);
BOARDOBJGRP_PMU_CONSTRUCT(pboardobjgrp, CLK, CLK_DOMAIN);
@@ -270,7 +270,7 @@ int clk_domain_sw_setup(struct gk20a *g)
(struct clk_domain_3x_slave *)pdomain;
pdomain_master =
(struct clk_domain_3x_master *)
(CLK_CLK_DOMAIN_GET((&g->clk_pmu),
(CLK_CLK_DOMAIN_GET((g->clk_pmu),
pdomain_slave->master_idx));
pdomain_master->slave_idxs_mask |= BIT(i);
}
@@ -289,7 +289,7 @@ int clk_domain_pmu_setup(struct gk20a *g)
nvgpu_log_info(g, " ");
pboardobjgrp = &g->clk_pmu.clk_domainobjs.super.super;
pboardobjgrp = &g->clk_pmu->clk_domainobjs.super.super;
if (!pboardobjgrp->bconstructed) {
return -EINVAL;
@@ -1070,7 +1070,7 @@ static int clk_domain_pmudatainit_35_prog(struct gk20a *g,
struct clk_domain_35_prog *pclk_domain_35_prog;
struct clk_domain_3x_prog *pclk_domain_3x_prog;
struct nv_pmu_clk_clk_domain_35_prog_boardobj_set *pset;
struct clk_domains *pdomains = &(g->clk_pmu.clk_domainobjs);
struct clk_domains *pdomains = &(g->clk_pmu->clk_domainobjs);
nvgpu_log_info(g, " ");
@@ -1109,7 +1109,7 @@ static int _clk_domain_pmudatainit_3x_prog(struct gk20a *g,
int status = 0;
struct clk_domain_3x_prog *pclk_domain_3x_prog;
struct nv_pmu_clk_clk_domain_30_prog_boardobj_set *pset;
struct clk_domains *pdomains = &(g->clk_pmu.clk_domainobjs);
struct clk_domains *pdomains = &(g->clk_pmu->clk_domainobjs);
nvgpu_log_info(g, " ");

12
drivers/gpu/nvgpu/clk/clk_fll.c
View File

@@ -128,14 +128,14 @@ int clk_fll_sw_setup(struct gk20a *g)
nvgpu_log_info(g, " ");
status = boardobjgrpconstruct_e32(g, &g->clk_pmu.avfs_fllobjs.super);
status = boardobjgrpconstruct_e32(g, &g->clk_pmu->avfs_fllobjs.super);
if (status != 0) {
nvgpu_err(g,
"error creating boardobjgrp for fll, status - 0x%x", status);
goto done;
}
pfllobjs = &(g->clk_pmu.avfs_fllobjs);
pboardobjgrp = &(g->clk_pmu.avfs_fllobjs.super.super);
pfllobjs = &(g->clk_pmu->avfs_fllobjs);
pboardobjgrp = &(g->clk_pmu->avfs_fllobjs.super.super);
BOARDOBJGRP_PMU_CONSTRUCT(pboardobjgrp, CLK, FLL_DEVICE);
@@ -165,7 +165,7 @@ int clk_fll_sw_setup(struct gk20a *g)
}
status = BOARDOBJGRP_PMU_CMD_GRP_GET_STATUS_CONSTRUCT(g,
&g->clk_pmu.avfs_fllobjs.super.super,
&g->clk_pmu->avfs_fllobjs.super.super,
clk, CLK, clk_fll_device, CLK_FLL_DEVICE);
if (status != 0) {
nvgpu_err(g,
@@ -217,7 +217,7 @@ int clk_fll_pmu_setup(struct gk20a *g)
nvgpu_log_info(g, " ");
pboardobjgrp = &g->clk_pmu.avfs_fllobjs.super.super;
pboardobjgrp = &g->clk_pmu->avfs_fllobjs.super.super;
if (!pboardobjgrp->bconstructed) {
return -EINVAL;
@@ -244,7 +244,7 @@ static int devinit_get_fll_device_table(struct gk20a *g,
struct vin_device *pvin_dev;
u32 desctablesize;
u32 vbios_domain = NV_PERF_DOMAIN_4X_CLOCK_DOMAIN_SKIP;
struct avfsvinobjs *pvinobjs = &g->clk_pmu.avfs_vinobjs;
struct avfsvinobjs *pvinobjs = &g->clk_pmu->avfs_vinobjs;
nvgpu_log_info(g, " ");

10
drivers/gpu/nvgpu/clk/clk_freq_controller.c
View File

@@ -240,7 +240,7 @@ static int clk_get_freq_controller_table(struct gk20a *g,
(u8)BIOS_GET_FIELD(entry.param0,
NV_VBIOS_FCT_1X_ENTRY_PARAM0_ID);
pclk_domain = CLK_CLK_DOMAIN_GET((&g->clk_pmu),
pclk_domain = CLK_CLK_DOMAIN_GET((g->clk_pmu),
(u32)entry.clk_domain_idx);
freq_controller_data.freq_controller.clk_domain =
pclk_domain->api_domain;
@@ -332,7 +332,7 @@ int clk_freq_controller_pmu_setup(struct gk20a *g)
nvgpu_log_info(g, " ");
pboardobjgrp = &g->clk_pmu.clk_freq_controllers.super.super;
pboardobjgrp = &g->clk_pmu->clk_freq_controllers.super.super;
if (!pboardobjgrp->bconstructed) {
return -EINVAL;
@@ -397,7 +397,7 @@ int clk_freq_controller_sw_setup(struct gk20a *g)
int status = 0;
struct boardobjgrp *pboardobjgrp = NULL;
struct clk_freq_controllers *pclk_freq_controllers;
struct avfsfllobjs *pfllobjs = &(g->clk_pmu.avfs_fllobjs);
struct avfsfllobjs *pfllobjs = &(g->clk_pmu->avfs_fllobjs);
struct fll_device *pfll;
struct clk_freq_controller *pclkfreqctrl;
u8 i;
@@ -405,7 +405,7 @@ int clk_freq_controller_sw_setup(struct gk20a *g)
nvgpu_log_info(g, " ");
pclk_freq_controllers = &g->clk_pmu.clk_freq_controllers;
pclk_freq_controllers = &g->clk_pmu->clk_freq_controllers;
status = boardobjgrpconstruct_e32(g, &pclk_freq_controllers->super);
if (status != 0) {
nvgpu_err(g,
@@ -414,7 +414,7 @@ int clk_freq_controller_sw_setup(struct gk20a *g)
goto done;
}
pboardobjgrp = &g->clk_pmu.clk_freq_controllers.super.super;
pboardobjgrp = &g->clk_pmu->clk_freq_controllers.super.super;
pboardobjgrp->pmudatainit = _clk_freq_controllers_pmudatainit;
pboardobjgrp->pmudatainstget =

34
drivers/gpu/nvgpu/clk/clk_prog.c
View File

@@ -96,7 +96,7 @@ int clk_prog_sw_setup(struct gk20a *g)
nvgpu_log_info(g, " ");
status = boardobjgrpconstruct_e255(g, &g->clk_pmu.clk_progobjs.super);
status = boardobjgrpconstruct_e255(g, &g->clk_pmu->clk_progobjs.super);
if (status != 0) {
nvgpu_err(g,
"error creating boardobjgrp for clk prog, status - 0x%x",
@@ -104,8 +104,8 @@ int clk_prog_sw_setup(struct gk20a *g)
goto done;
}
pboardobjgrp = &g->clk_pmu.clk_progobjs.super.super;
pclkprogobjs = &(g->clk_pmu.clk_progobjs);
pboardobjgrp = &g->clk_pmu->clk_progobjs.super.super;
pclkprogobjs = &(g->clk_pmu->clk_progobjs);
BOARDOBJGRP_PMU_CONSTRUCT(pboardobjgrp, CLK, CLK_PROG);
@@ -127,7 +127,7 @@ int clk_prog_sw_setup(struct gk20a *g)
goto done;
}
status = clk_domain_clk_prog_link(g, &g->clk_pmu);
status = clk_domain_clk_prog_link(g, g->clk_pmu);
if (status != 0) {
nvgpu_err(g, "error constructing VF point board objects");
goto done;
@@ -145,7 +145,7 @@ int clk_prog_pmu_setup(struct gk20a *g)
nvgpu_log_info(g, " ");
pboardobjgrp = &g->clk_pmu.clk_progobjs.super.super;
pboardobjgrp = &g->clk_pmu->clk_progobjs.super.super;
if (!pboardobjgrp->bconstructed) {
return -EINVAL;
@@ -719,7 +719,7 @@ static int clk_prog_pmudatainit_1x_master(struct gk20a *g,
struct clk_prog_1x_master *pclk_prog_1x_master;
struct nv_pmu_clk_clk_prog_1x_master_boardobj_set *pset;
size_t vfsize = sizeof(struct ctrl_clk_clk_prog_1x_master_vf_entry) *
g->clk_pmu.clk_progobjs.vf_entry_count;
g->clk_pmu->clk_progobjs.vf_entry_count;
nvgpu_log_info(g, " ");
@@ -752,7 +752,7 @@ static int clk_prog_pmudatainit_35_master(struct gk20a *g,
struct nv_pmu_clk_clk_prog_35_master_boardobj_set *pset;
size_t voltrail_sec_vfsize =
sizeof(struct ctrl_clk_clk_prog_35_master_sec_vf_entry_voltrail)
* g->clk_pmu.clk_progobjs.vf_sec_entry_count;
* g->clk_pmu->clk_progobjs.vf_sec_entry_count;
nvgpu_log_info(g, " ");
@@ -779,7 +779,7 @@ static int clk_prog_pmudatainit_1x_master_ratio(struct gk20a *g,
struct clk_prog_1x_master_ratio *pclk_prog_1x_master_ratio;
struct nv_pmu_clk_clk_prog_1x_master_ratio_boardobj_set *pset;
size_t slavesize = sizeof(struct ctrl_clk_clk_prog_1x_master_ratio_slave_entry) *
g->clk_pmu.clk_progobjs.slave_entry_count;
g->clk_pmu->clk_progobjs.slave_entry_count;
nvgpu_log_info(g, " ");
@@ -808,7 +808,7 @@ static int clk_prog_pmudatainit_35_master_ratio(struct gk20a *g,
struct clk_prog_35_master_ratio *pclk_prog_35_master_ratio;
struct nv_pmu_clk_clk_prog_35_master_ratio_boardobj_set *pset;
size_t slavesize = sizeof(struct ctrl_clk_clk_prog_1x_master_ratio_slave_entry) *
g->clk_pmu.clk_progobjs.slave_entry_count;
g->clk_pmu->clk_progobjs.slave_entry_count;
nvgpu_log_info(g, " ");
@@ -838,7 +838,7 @@ static int clk_prog_pmudatainit_1x_master_table(struct gk20a *g,
struct clk_prog_1x_master_table *pclk_prog_1x_master_table;
struct nv_pmu_clk_clk_prog_1x_master_table_boardobj_set *pset;
size_t slavesize = sizeof(struct ctrl_clk_clk_prog_1x_master_ratio_slave_entry) *
g->clk_pmu.clk_progobjs.slave_entry_count;
g->clk_pmu->clk_progobjs.slave_entry_count;
nvgpu_log_info(g, " ");
@@ -866,7 +866,7 @@ static int clk_prog_pmudatainit_35_master_table(struct gk20a *g,
struct clk_prog_35_master_table *pclk_prog_35_master_table;
struct nv_pmu_clk_clk_prog_35_master_table_boardobj_set *pset;
size_t slavesize = sizeof(struct ctrl_clk_clk_prog_1x_master_ratio_slave_entry) *
g->clk_pmu.clk_progobjs.slave_entry_count;
g->clk_pmu->clk_progobjs.slave_entry_count;
nvgpu_log_info(g, " ");
@@ -1008,7 +1008,7 @@ static int clk_prog_construct_1x_master(struct gk20a *g,
(struct clk_prog_1x_master *)pargs;
int status = 0;
size_t vfsize = sizeof(struct ctrl_clk_clk_prog_1x_master_vf_entry) *
g->clk_pmu.clk_progobjs.vf_entry_count;
g->clk_pmu->clk_progobjs.vf_entry_count;
u8 railidx;
nvgpu_log_info(g, " type - %x", BOARDOBJ_GET_TYPE(pargs));
@@ -1045,7 +1045,7 @@ static int clk_prog_construct_1x_master(struct gk20a *g,
pclkprog->b_o_c_o_v_enabled = ptmpprog->b_o_c_o_v_enabled;
for (railidx = 0;
railidx < g->clk_pmu.clk_progobjs.vf_entry_count;
railidx < g->clk_pmu->clk_progobjs.vf_entry_count;
railidx++) {
pclkprog->p_vf_entries[railidx].vf_point_idx_first =
CTRL_CLK_CLK_VF_POINT_IDX_INVALID;
@@ -1105,7 +1105,7 @@ static int clk_prog_construct_1x_master_ratio(struct gk20a *g,
(struct clk_prog_1x_master_ratio *)pargs;
int status = 0;
size_t slavesize = sizeof(struct ctrl_clk_clk_prog_1x_master_ratio_slave_entry) *
g->clk_pmu.clk_progobjs.slave_entry_count;
g->clk_pmu->clk_progobjs.slave_entry_count;
if (BOARDOBJ_GET_TYPE(pargs) != CTRL_CLK_CLK_PROG_TYPE_1X_MASTER_RATIO) {
return -EINVAL;
@@ -1148,7 +1148,7 @@ static int clk_prog_construct_35_master_ratio(struct gk20a *g,
(struct clk_prog_35_master_ratio *)pargs;
int status = 0;
size_t slavesize = sizeof(struct ctrl_clk_clk_prog_1x_master_ratio_slave_entry) *
g->clk_pmu.clk_progobjs.slave_entry_count;
g->clk_pmu->clk_progobjs.slave_entry_count;
if (BOARDOBJ_GET_TYPE(pargs) != CTRL_CLK_CLK_PROG_TYPE_35_MASTER_RATIO) {
return -EINVAL;
@@ -1191,7 +1191,7 @@ static int clk_prog_construct_1x_master_table(struct gk20a *g,
(struct clk_prog_1x_master_table *)pargs;
int status = 0;
size_t slavesize = sizeof(struct ctrl_clk_clk_prog_1x_master_ratio_slave_entry) *
g->clk_pmu.clk_progobjs.slave_entry_count;
g->clk_pmu->clk_progobjs.slave_entry_count;
nvgpu_log_info(g, "type - %x", BOARDOBJ_GET_TYPE(pargs));
@@ -1243,7 +1243,7 @@ static int clk_prog_construct_35_master_table(struct gk20a *g,
(struct clk_prog_35_master_table *)pargs;
int status = 0;
size_t slavesize = sizeof(struct ctrl_clk_clk_prog_1x_master_table_slave_entry) *
g->clk_pmu.clk_progobjs.slave_entry_count;
g->clk_pmu->clk_progobjs.slave_entry_count;
nvgpu_log_info(g, "type - %x", BOARDOBJ_GET_TYPE(pargs));

10
drivers/gpu/nvgpu/clk/clk_vf_point.c
View File

@@ -99,7 +99,7 @@ int clk_vf_point_sw_setup(struct gk20a *g)
nvgpu_log_info(g, " ");
status = boardobjgrpconstruct_e255(g, &g->clk_pmu.clk_vf_pointobjs.super);
status = boardobjgrpconstruct_e255(g, &g->clk_pmu->clk_vf_pointobjs.super);
if (status != 0) {
nvgpu_err(g,
"error creating boardobjgrp for clk vfpoint, status - 0x%x",
@@ -107,7 +107,7 @@ int clk_vf_point_sw_setup(struct gk20a *g)
goto done;
}
pboardobjgrp = &g->clk_pmu.clk_vf_pointobjs.super.super;
pboardobjgrp = &g->clk_pmu->clk_vf_pointobjs.super.super;
BOARDOBJGRP_PMU_CONSTRUCT(pboardobjgrp, CLK, CLK_VF_POINT);
@@ -121,7 +121,7 @@ int clk_vf_point_sw_setup(struct gk20a *g)
}
status = BOARDOBJGRP_PMU_CMD_GRP_GET_STATUS_CONSTRUCT(g,
&g->clk_pmu.clk_vf_pointobjs.super.super,
&g->clk_pmu->clk_vf_pointobjs.super.super,
clk, CLK, clk_vf_point, CLK_VF_POINT);
if (status != 0) {
nvgpu_err(g,
@@ -146,7 +146,7 @@ int clk_vf_point_pmu_setup(struct gk20a *g)
nvgpu_log_info(g, " ");
pboardobjgrp = &g->clk_pmu.clk_vf_pointobjs.super.super;
pboardobjgrp = &g->clk_pmu->clk_vf_pointobjs.super.super;
if (!pboardobjgrp->bconstructed) {
return -EINVAL;
@@ -402,7 +402,7 @@ int clk_vf_point_cache(struct gk20a *g)
u8 index;
nvgpu_log_info(g, " ");
pclk_vf_points = &g->clk_pmu.clk_vf_pointobjs;
pclk_vf_points = &g->clk_pmu->clk_vf_pointobjs;
pboardobjgrp = &pclk_vf_points->super.super;
pboardobjgrpmask = &pclk_vf_points->super.mask.super;

12
drivers/gpu/nvgpu/clk/clk_vin.c
View File

@@ -188,7 +188,7 @@ int clk_vin_sw_setup(struct gk20a *g)
nvgpu_log_info(g, " ");
status = boardobjgrpconstruct_e32(g, &g->clk_pmu.avfs_vinobjs.super);
status = boardobjgrpconstruct_e32(g, &g->clk_pmu->avfs_vinobjs.super);
if (status != 0) {
nvgpu_err(g,
"error creating boardobjgrp for clk vin, statu - 0x%x",
@@ -196,8 +196,8 @@ int clk_vin_sw_setup(struct gk20a *g)
goto done;
}
pboardobjgrp = &g->clk_pmu.avfs_vinobjs.super.super;
pvinobjs = &g->clk_pmu.avfs_vinobjs;
pboardobjgrp = &g->clk_pmu->avfs_vinobjs.super.super;
pvinobjs = &g->clk_pmu->avfs_vinobjs;
BOARDOBJGRP_PMU_CONSTRUCT(pboardobjgrp, CLK, VIN_DEVICE);
@@ -214,7 +214,7 @@ int clk_vin_sw_setup(struct gk20a *g)
pboardobjgrp->pmudatainstget = _clk_vin_devgrp_pmudata_instget;
pboardobjgrp->pmustatusinstget = _clk_vin_devgrp_pmustatus_instget;
status = devinit_get_vin_device_table(g, &g->clk_pmu.avfs_vinobjs);
status = devinit_get_vin_device_table(g, &g->clk_pmu->avfs_vinobjs);
if (status != 0) {
goto done;
}
@@ -223,7 +223,7 @@ int clk_vin_sw_setup(struct gk20a *g)
g->ops.pmu_ver.clk.clk_avfs_get_vin_cal_data(g, pvinobjs, pvindev);
status = BOARDOBJGRP_PMU_CMD_GRP_GET_STATUS_CONSTRUCT(g,
&g->clk_pmu.avfs_vinobjs.super.super,
&g->clk_pmu->avfs_vinobjs.super.super,
clk, CLK, clk_vin_device, CLK_VIN_DEVICE);
if (status != 0) {
nvgpu_err(g,
@@ -244,7 +244,7 @@ int clk_vin_pmu_setup(struct gk20a *g)
nvgpu_log_info(g, " ");
pboardobjgrp = &g->clk_pmu.avfs_vinobjs.super.super;
pboardobjgrp = &g->clk_pmu->avfs_vinobjs.super.super;
if (!pboardobjgrp->bconstructed) {
return -EINVAL;

2
drivers/gpu/nvgpu/gp106/clk_arb_gp106.c
View File

@@ -45,7 +45,7 @@ int gp106_get_arbiter_clk_range(struct gk20a *g, u32 api_domain,
enum nv_pmu_clk_clkwhich clkwhich;
struct clk_set_info *p0_info;
struct clk_set_info *p5_info;
struct avfsfllobjs *pfllobjs = &(g->clk_pmu.avfs_fllobjs);
struct avfsfllobjs *pfllobjs = &(g->clk_pmu->avfs_fllobjs);
u16 limit_min_mhz;

2
drivers/gpu/nvgpu/gp106/clk_gp106.c
View File

@@ -258,7 +258,7 @@ int gp106_clk_domain_get_f_points(
int status = -EINVAL;
struct clk_domain *pdomain;
u8 i;
struct clk_pmupstate *pclk = &g->clk_pmu;
struct clk_pmupstate *pclk = g->clk_pmu;
if (pfpointscount == NULL) {
return -EINVAL;

10
drivers/gpu/nvgpu/gp106/mclk_gp106.c
View File

@@ -3228,7 +3228,7 @@ done:
void gp106_mclk_deinit(struct gk20a *g)
{
struct clk_mclk_state *mclk = &g->clk_pmu.clk_mclk;
struct clk_mclk_state *mclk = &g->clk_pmu->clk_mclk;
nvgpu_mutex_destroy(&mclk->data_lock);
nvgpu_mutex_destroy(&mclk->mclk_lock);
@@ -3246,7 +3246,7 @@ int gp106_mclk_init(struct gk20a *g)
nvgpu_log_fn(g, " ");
mclk = &g->clk_pmu.clk_mclk;
mclk = &g->clk_pmu->clk_mclk;
err = nvgpu_mutex_init(&mclk->mclk_lock);
if (err != 0) {
@@ -3354,7 +3354,7 @@ int gp106_mclk_change(struct gk20a *g, u16 val)
(void) memset(&payload, 0, sizeof(struct pmu_payload));
mclk = &g->clk_pmu.clk_mclk;
mclk = &g->clk_pmu->clk_mclk;
nvgpu_mutex_acquire(&mclk->mclk_lock);
@@ -3483,7 +3483,7 @@ static int mclk_debug_speed_set(void *data, u64 val)
struct gk20a *g = (struct gk20a *) data;
struct clk_mclk_state *mclk;
mclk = &g->clk_pmu.clk_mclk;
mclk = &g->clk_pmu->clk_mclk;
/* This is problematic because it can interrupt the arbiter
* and send it to sleep. we need to consider removing this
@@ -3508,7 +3508,7 @@ static int mclk_switch_stats_show(struct seq_file *s, void *unused)
u64 num;
s64 tmp, avg, std, max, min;
mclk = &g->clk_pmu.clk_mclk;
mclk = &g->clk_pmu->clk_mclk;
/* Make copy of structure to reduce time with lock held */
nvgpu_mutex_acquire(&mclk->data_lock);

4
drivers/gpu/nvgpu/include/nvgpu/gk20a.h
View File

@@ -50,6 +50,7 @@ struct nvgpu_gpu_ctxsw_trace_filter;
#endif
struct priv_cmd_entry;
struct nvgpu_setup_bind_args;
struct clk_pmupstate;
#include <nvgpu/lock.h>
#include <nvgpu/thread.h>
@@ -74,7 +75,6 @@ struct nvgpu_setup_bind_args;
#include "gk20a/clk_gk20a.h"
#include "gk20a/fifo_gk20a.h"
#include "gk20a/gr_gk20a.h"
#include "clk/clk.h"
#include "pmu_perf/pmu_perf.h"
#include "pmgr/pmgr.h"
#include "therm/thrm.h"
@@ -1490,7 +1490,7 @@ struct gk20a {
struct nvgpu_pmu pmu;
struct nvgpu_acr acr;
struct nvgpu_ecc ecc;
struct clk_pmupstate clk_pmu;
struct clk_pmupstate *clk_pmu;
struct perf_pmupstate perf_pmu;
struct pmgr_pmupstate pmgr_pmu;
struct therm_pmupstate therm_pmu;

9
drivers/gpu/nvgpu/os/linux/debug_clk_gp106.c
View File

@@ -19,6 +19,7 @@
#include <nvgpu/clk.h>
#include "os_linux.h"
#include "clk/clk.h"
void nvgpu_clk_arb_pstate_change_lock(struct gk20a *g, bool lock);
@@ -41,7 +42,7 @@ static int sys_cfc_read(void *data , u64 *val)
{
struct gk20a *g = (struct gk20a *)data;
bool bload = boardobjgrpmask_bitget(
&g->clk_pmu.clk_freq_controllers.freq_ctrl_load_mask.super,
&g->clk_pmu->clk_freq_controllers.freq_ctrl_load_mask.super,
CTRL_CLK_CLK_FREQ_CONTROLLER_ID_SYS);
/* val = 1 implies CLFC is loaded or enabled */
@@ -68,7 +69,7 @@ static int ltc_cfc_read(void *data , u64 *val)
{
struct gk20a *g = (struct gk20a *)data;
bool bload = boardobjgrpmask_bitget(
&g->clk_pmu.clk_freq_controllers.freq_ctrl_load_mask.super,
&g->clk_pmu->clk_freq_controllers.freq_ctrl_load_mask.super,
CTRL_CLK_CLK_FREQ_CONTROLLER_ID_LTC);
/* val = 1 implies CLFC is loaded or enabled */
@@ -95,7 +96,7 @@ static int xbar_cfc_read(void *data , u64 *val)
{
struct gk20a *g = (struct gk20a *)data;
bool bload = boardobjgrpmask_bitget(
&g->clk_pmu.clk_freq_controllers.freq_ctrl_load_mask.super,
&g->clk_pmu->clk_freq_controllers.freq_ctrl_load_mask.super,
CTRL_CLK_CLK_FREQ_CONTROLLER_ID_XBAR);
/* val = 1 implies CLFC is loaded or enabled */
@@ -123,7 +124,7 @@ static int gpc_cfc_read(void *data , u64 *val)
{
struct gk20a *g = (struct gk20a *)data;
bool bload = boardobjgrpmask_bitget(
&g->clk_pmu.clk_freq_controllers.freq_ctrl_load_mask.super,
&g->clk_pmu->clk_freq_controllers.freq_ctrl_load_mask.super,
CTRL_CLK_CLK_FREQ_CONTROLLER_ID_GPC0);
/* val = 1 implies CLFC is loaded or enabled */

9
drivers/gpu/nvgpu/os/linux/debug_clk_gv100.c
View File

@@ -18,6 +18,7 @@
#include <nvgpu/clk.h>
#include "clk/clk.h"
#include "gv100/clk_gv100.h"
#include "os_linux.h"
@@ -43,7 +44,7 @@ static int sys_cfc_read(void *data , u64 *val)
{
struct gk20a *g = (struct gk20a *)data;
bool bload = boardobjgrpmask_bitget(
&g->clk_pmu.clk_freq_controllers.freq_ctrl_load_mask.super,
&g->clk_pmu->clk_freq_controllers.freq_ctrl_load_mask.super,
CTRL_CLK_CLK_FREQ_CONTROLLER_ID_SYS);
/* val = 1 implies CLFC is loaded or enabled */
@@ -70,7 +71,7 @@ static int ltc_cfc_read(void *data , u64 *val)
{
struct gk20a *g = (struct gk20a *)data;
bool bload = boardobjgrpmask_bitget(
&g->clk_pmu.clk_freq_controllers.freq_ctrl_load_mask.super,
&g->clk_pmu->clk_freq_controllers.freq_ctrl_load_mask.super,
CTRL_CLK_CLK_FREQ_CONTROLLER_ID_LTC);
/* val = 1 implies CLFC is loaded or enabled */
@@ -97,7 +98,7 @@ static int xbar_cfc_read(void *data , u64 *val)
{
struct gk20a *g = (struct gk20a *)data;
bool bload = boardobjgrpmask_bitget(
&g->clk_pmu.clk_freq_controllers.freq_ctrl_load_mask.super,
&g->clk_pmu->clk_freq_controllers.freq_ctrl_load_mask.super,
CTRL_CLK_CLK_FREQ_CONTROLLER_ID_XBAR);
/* val = 1 implies CLFC is loaded or enabled */
@@ -125,7 +126,7 @@ static int gpc_cfc_read(void *data , u64 *val)
{
struct gk20a *g = (struct gk20a *)data;
bool bload = boardobjgrpmask_bitget(
&g->clk_pmu.clk_freq_controllers.freq_ctrl_load_mask.super,
&g->clk_pmu->clk_freq_controllers.freq_ctrl_load_mask.super,
CTRL_CLK_CLK_FREQ_CONTROLLER_ID_GPC0);
/* val = 1 implies CLFC is loaded or enabled */

2
drivers/gpu/nvgpu/pmu_perf/vfe_var.h
View File

@@ -24,6 +24,8 @@
#define NVGPU_PERF_VFE_VAR_H
#include <nvgpu/boardobjgrp.h>
#include <nvgpu/boardobjgrp_e32.h>
#include <nvgpu/boardobjgrp_e255.h>
#include <nvgpu/pmuif/nvgpu_gpmu_cmdif.h>
int vfe_var_sw_setup(struct gk20a *g);

43
drivers/gpu/nvgpu/pstate/pstate.c
View File

@@ -36,6 +36,8 @@ static int pstate_sw_setup(struct gk20a *g);
void gk20a_deinit_pstate_support(struct gk20a *g)
{
clk_free_pmupstate(g);
if (g->ops.clk.mclk_deinit != NULL) {
g->ops.clk.mclk_deinit(g);
}
@@ -50,87 +52,96 @@ int gk20a_init_pstate_support(struct gk20a *g)
nvgpu_log_fn(g, " ");
err = volt_rail_sw_setup(g);
err = clk_init_pmupstate(g);
if (err != 0) {
return err;
}
err = volt_rail_sw_setup(g);
if (err != 0) {
goto err_clk_init_pmupstate;
}
err = volt_dev_sw_setup(g);
if (err != 0) {
return err;
goto err_clk_init_pmupstate;
}
err = volt_policy_sw_setup(g);
if (err != 0) {
return err;
goto err_clk_init_pmupstate;
}
err = clk_vin_sw_setup(g);
if (err != 0) {
return err;
goto err_clk_init_pmupstate;
}
err = clk_fll_sw_setup(g);
if (err != 0) {
return err;
goto err_clk_init_pmupstate;
}
err = therm_domain_sw_setup(g);
if (err != 0) {
return err;
goto err_clk_init_pmupstate;
}
err = vfe_var_sw_setup(g);
if (err != 0) {
return err;
goto err_clk_init_pmupstate;
}
err = vfe_equ_sw_setup(g);
if (err != 0) {
return err;
goto err_clk_init_pmupstate;
}
err = clk_domain_sw_setup(g);
if (err != 0) {
return err;
goto err_clk_init_pmupstate;
}
err = clk_vf_point_sw_setup(g);
if (err != 0) {
return err;
goto err_clk_init_pmupstate;
}
err = clk_prog_sw_setup(g);
if (err != 0) {
return err;
goto err_clk_init_pmupstate;
}
err = pstate_sw_setup(g);
if (err != 0) {
return err;
goto err_clk_init_pmupstate;
}
if(g->ops.clk.support_pmgr_domain) {
err = pmgr_domain_sw_setup(g);
if (err != 0) {
return err;
goto err_clk_init_pmupstate;
}
}
if (g->ops.clk.support_clk_freq_controller) {
err = clk_freq_controller_sw_setup(g);
if (err != 0) {
return err;
goto err_clk_init_pmupstate;
}
}
if(g->ops.clk.support_lpwr_pg) {
err = nvgpu_lpwr_pg_setup(g);
if (err != 0) {
return err;
goto err_clk_init_pmupstate;
}
}
return 0;
err_clk_init_pmupstate:
clk_free_pmupstate(g);
return err;
}
@@ -328,7 +339,7 @@ static int parse_pstate_entry_5x(struct gk20a *g,
struct clk_domain *clk_domain;
clk_domain = (struct clk_domain *)BOARDOBJGRP_OBJ_GET_BY_IDX(
&g->clk_pmu.clk_domainobjs.super.super, clkidx);
&g->clk_pmu->clk_domainobjs.super.super, clkidx);
pclksetinfo = &pstate->clklist.clksetinfo[clkidx];
clk_entry = (struct vbios_pstate_entry_clock_5x *)p;