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gpu: nvgpu: Fix clk_gp106.h and clk_gv100.h headers

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clk_gp106.h and clk_gv100.h define conflicting symbols, which prevent
including them both at the same time. One of the conflicting structs
is namemap_cfg, which has different definitions in clk_gp106.h and
include/nvgpu/clk.h.

Move all constants used only by clk_*.c to be defined there, delete
the extra namemap_cfg structure definition, and modify code to cope
with the unified namemap_cfg.

JIRa NVGPU-596

Change-Id: Id68919da4567ec1507eda0cfaa19bf047a7bfc59
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1945285
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Terje Bergstrom
2018-11-07 15:07:08 -08:00
committed by mobile promotions
parent 5dd5c0aa94
commit bca27e31e3
6 changed files with 37 additions and 49 deletions
Download Patch File Download Diff File Expand all files Collapse all files

26
drivers/gpu/nvgpu/gp106/clk_gp106.c
View File

@@ -37,9 +37,21 @@
#include <nvgpu/hw/gp106/hw_trim_gp106.h>
#define CLK_NAMEMAP_INDEX_GPC2CLK 0x00
#define CLK_NAMEMAP_INDEX_XBAR2CLK 0x02
#define CLK_NAMEMAP_INDEX_SYS2CLK 0x07 /* SYSPLL */
#define CLK_NAMEMAP_INDEX_DRAMCLK 0x20 /* DRAMPLL */
#define CLK_DEFAULT_CNTRL_SETTLE_RETRIES 10
#define CLK_DEFAULT_CNTRL_SETTLE_USECS 5
#define NUM_NAMEMAPS 4
#define XTAL4X_KHZ 108000
#define XTAL_CNTR_CLKS 27000 /* 1000usec at 27KHz XTAL */
#define XTAL_CNTR_DELAY 1000 /* we need acuracy up to the ms */
#define XTAL_SCALE_TO_KHZ 1
u32 gp106_crystal_clk_hz(struct gk20a *g)
{
return (XTAL4X_KHZ * 1000);
@@ -110,7 +122,7 @@ int gp106_init_clk_support(struct gk20a *g)
.cntr = {
.reg_ctrl_addr = trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_r(),
.reg_ctrl_idx = trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_source_gpc2clk_f(),
.reg_cntr_addr = trim_gpc_bcast_clk_cntr_ncgpcclk_cnt_r()
.reg_cntr_addr[0] = trim_gpc_bcast_clk_cntr_ncgpcclk_cnt_r()
},
.name = "gpc2clk",
.scale = 1
@@ -125,7 +137,7 @@ int gp106_init_clk_support(struct gk20a *g)
.cntr = {
.reg_ctrl_addr = trim_sys_clk_cntr_ncsyspll_cfg_r(),
.reg_ctrl_idx = trim_sys_clk_cntr_ncsyspll_cfg_source_sys2clk_f(),
.reg_cntr_addr = trim_sys_clk_cntr_ncsyspll_cnt_r()
.reg_cntr_addr[0] = trim_sys_clk_cntr_ncsyspll_cnt_r()
},
.name = "sys2clk",
.scale = 1
@@ -140,7 +152,7 @@ int gp106_init_clk_support(struct gk20a *g)
.cntr = {
.reg_ctrl_addr = trim_sys_clk_cntr_ncltcpll_cfg_r(),
.reg_ctrl_idx = trim_sys_clk_cntr_ncltcpll_cfg_source_xbar2clk_f(),
.reg_cntr_addr = trim_sys_clk_cntr_ncltcpll_cnt_r()
.reg_cntr_addr[0] = trim_sys_clk_cntr_ncltcpll_cnt_r()
},
.name = "xbar2clk",
.scale = 1
@@ -155,7 +167,7 @@ int gp106_init_clk_support(struct gk20a *g)
.cntr = {
.reg_ctrl_addr = trim_fbpa_bcast_clk_cntr_ncltcclk_cfg_r(),
.reg_ctrl_idx = trim_fbpa_bcast_clk_cntr_ncltcclk_cfg_source_dramdiv4_rec_clk1_f(),
.reg_cntr_addr = trim_fbpa_bcast_clk_cntr_ncltcclk_cnt_r()
.reg_cntr_addr[0] = trim_fbpa_bcast_clk_cntr_ncltcclk_cnt_r()
},
.name = "dramdiv4_rec_clk1",
.scale = 4
@@ -179,7 +191,7 @@ u32 gp106_get_rate_cntr(struct gk20a *g, struct namemap_cfg *c)
if ((c == NULL) ||
(c->cntr.reg_ctrl_addr == 0U) ||
(c->cntr.reg_cntr_addr == 0U)) {
(c->cntr.reg_cntr_addr[0] == 0U)) {
return 0;
}
@@ -200,7 +212,7 @@ u32 gp106_get_rate_cntr(struct gk20a *g, struct namemap_cfg *c)
retries = CLK_DEFAULT_CNTRL_SETTLE_RETRIES;
do {
nvgpu_udelay(CLK_DEFAULT_CNTRL_SETTLE_USECS);
cntr = gk20a_readl(g, c->cntr.reg_cntr_addr);
cntr = gk20a_readl(g, c->cntr.reg_cntr_addr[0]);
retries--;
} while ((retries != 0U) && (cntr != 0U));
@@ -221,7 +233,7 @@ u32 gp106_get_rate_cntr(struct gk20a *g, struct namemap_cfg *c)
nvgpu_udelay(XTAL_CNTR_DELAY);
cntr = XTAL_SCALE_TO_KHZ * gk20a_readl(g, c->cntr.reg_cntr_addr);
cntr = XTAL_SCALE_TO_KHZ * gk20a_readl(g, c->cntr.reg_cntr_addr[0]);
read_err:
/* reset and restore control register */

12
drivers/gpu/nvgpu/gp106/clk_gp106.h
View File

@@ -25,18 +25,6 @@
#include <nvgpu/lock.h>
#include <nvgpu/clk.h>
#define CLK_NAMEMAP_INDEX_GPC2CLK 0x00
#define CLK_NAMEMAP_INDEX_XBAR2CLK 0x02
#define CLK_NAMEMAP_INDEX_SYS2CLK 0x07 /* SYSPLL */
#define CLK_NAMEMAP_INDEX_DRAMCLK 0x20 /* DRAMPLL */
#define CLK_DEFAULT_CNTRL_SETTLE_RETRIES 10
#define CLK_DEFAULT_CNTRL_SETTLE_USECS 5
#define XTAL_CNTR_CLKS 27000 /* 1000usec at 27KHz XTAL */
#define XTAL_CNTR_DELAY 1000 /* we need acuracy up to the ms */
#define XTAL_SCALE_TO_KHZ 1
u32 gp106_get_rate_cntr(struct gk20a *g, struct namemap_cfg *c);
int gp106_init_clk_support(struct gk20a *g);
u32 gp106_crystal_clk_hz(struct gk20a *g);

14
drivers/gpu/nvgpu/gv100/clk_gv100.c
View File

@@ -33,11 +33,25 @@
#include <nvgpu/clk_arb.h>
#include <nvgpu/timers.h>
#include <nvgpu/gk20a.h>
#include <nvgpu/clk.h>
#include "clk_gv100.h"
#include <nvgpu/hw/gv100/hw_trim_gv100.h>
#define CLK_NAMEMAP_INDEX_GPCCLK 0x00
#define CLK_NAMEMAP_INDEX_XBARCLK 0x02
#define CLK_NAMEMAP_INDEX_SYSCLK 0x07 /* SYSPLL */
#define CLK_NAMEMAP_INDEX_DRAMCLK 0x20 /* DRAMPLL */
#define CLK_DEFAULT_CNTRL_SETTLE_RETRIES 10
#define CLK_DEFAULT_CNTRL_SETTLE_USECS 5
#define XTAL_CNTR_CLKS 27000 /* 1000usec at 27KHz XTAL */
#define XTAL_CNTR_DELAY 10000 /* we need acuracy up to the 10ms */
#define XTAL_SCALE_TO_KHZ 1
#define NUM_NAMEMAPS (3U)
#define XTAL4X_KHZ 108000
u32 gv100_crystal_clk_hz(struct gk20a *g)
{

29
drivers/gpu/nvgpu/gv100/clk_gv100.h
View File

@@ -25,36 +25,7 @@
#include <nvgpu/lock.h>
#include <nvgpu/gk20a.h>
#define CLK_NAMEMAP_INDEX_GPCCLK 0x00
#define CLK_NAMEMAP_INDEX_XBARCLK 0x02
#define CLK_NAMEMAP_INDEX_SYSCLK 0x07 /* SYSPLL */
#define CLK_NAMEMAP_INDEX_DRAMCLK 0x20 /* DRAMPLL */
#define CLK_DEFAULT_CNTRL_SETTLE_RETRIES 10
#define CLK_DEFAULT_CNTRL_SETTLE_USECS 5
#define CLK_MAX_CNTRL_REGISTERS 2
#define XTAL_CNTR_CLKS 27000 /* 1000usec at 27KHz XTAL */
#define XTAL_CNTR_DELAY 10000 /* we need acuracy up to the 10ms */
#define XTAL_SCALE_TO_KHZ 1
#define NUM_NAMEMAPS (3U)
#define XTAL4X_KHZ 108000
u32 gv100_get_rate_cntr(struct gk20a *g, struct namemap_cfg *c);
struct namemap_cfg {
u32 namemap;
u32 is_enable; /* Namemap enabled */
u32 is_counter; /* Using cntr */
struct gk20a *g;
struct {
u32 reg_ctrl_addr;
u32 reg_ctrl_idx;
u32 reg_cntr_addr[CLK_MAX_CNTRL_REGISTERS];
} cntr;
u32 scale;
char name[24];
};
int gv100_init_clk_support(struct gk20a *g);
u32 gv100_crystal_clk_hz(struct gk20a *g);
unsigned long gv100_clk_measure_freq(struct gk20a *g, u32 api_domain);

3
drivers/gpu/nvgpu/include/nvgpu/clk.h
View File

@@ -24,6 +24,7 @@
#define NVGPU_INCLUDE_CLK_H
#define CLK_NAME_MAX 24
#define CLK_MAX_CNTRL_REGISTERS 2
struct namemap_cfg {
u32 namemap;
@@ -33,7 +34,7 @@ struct namemap_cfg {
struct {
u32 reg_ctrl_addr;
u32 reg_ctrl_idx;
u32 reg_cntr_addr;
u32 reg_cntr_addr[CLK_MAX_CNTRL_REGISTERS];
} cntr;
u32 scale;
char name[CLK_NAME_MAX];

2
drivers/gpu/nvgpu/os/linux/debug_clk_gv100.c
View File

@@ -16,6 +16,8 @@
#include <linux/debugfs.h>
#include <nvgpu/clk.h>
#include "gv100/clk_gv100.h"
#include "os_linux.h"