gpu: nvgpu: Cleanup generic MM code

t19x changes necessary for change in core MM code.

JIRA NVGPU-30

Change-Id: I62f419450c1a33d0826390d7cbb5ad93569f8c89
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1577265
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: David Martinez Nieto <dmartineznie@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>

drivers/gpu/nvgpu/gv100/hal_gv100.c

@@ -535,6 +535,7 @@ static const struct gpu_ops gv100_ops = {
 		.init_pdb = gp10b_mm_init_pdb,
 		.init_mm_setup_hw = gv11b_init_mm_setup_hw,
 		.is_bar1_supported = gv11b_mm_is_bar1_supported,
+		.alloc_inst_block = gk20a_alloc_inst_block,
 		.init_inst_block = gv11b_init_inst_block,
 		.mmu_fault_pending = gv11b_mm_mmu_fault_pending,
 		.get_kind_invalid = gm20b_get_kind_invalid,

drivers/gpu/nvgpu/gv11b/acr_gv11b.c

@@ -35,6 +35,7 @@
 #include <nvgpu/nvgpu_mem.h>
 #include <nvgpu/acr/nvgpu_acr.h>
 #include <nvgpu/firmware.h>
+#include <nvgpu/mm.h>
 
 #include "gk20a/gk20a.h"
 #include "acr_gv11b.h"
@@ -211,7 +212,7 @@ static int bl_bootstrap(struct nvgpu_pmu *pmu,
 			pwr_falcon_itfen_ctxen_enable_f());
 	gk20a_writel(g, pwr_pmu_new_instblk_r(),
 		pwr_pmu_new_instblk_ptr_f(
-		gk20a_mm_inst_block_addr(g, &mm->pmu.inst_block) >> 12) |
+		nvgpu_inst_block_addr(g, &mm->pmu.inst_block) >> 12) |
 		pwr_pmu_new_instblk_valid_f(1) |
 		pwr_pmu_new_instblk_target_sys_ncoh_f());
 
@@ -291,4 +292,3 @@ int gv11b_init_pmu_setup_hw1(struct gk20a *g,
 		return err;
 	return 0;
 }
-

drivers/gpu/nvgpu/gv11b/css_gr_gv11b.c

@@ -135,8 +135,7 @@ int gv11b_css_hw_enable_snapshot(struct channel_gk20a *ch,
 	gk20a_writel(g, perf_pmasys_outsize_r(), snapshot_size);
 
 	/* this field is aligned to 4K */
-	inst_pa_page = gk20a_mm_inst_block_addr(g,
-					&g->mm.hwpm.inst_block) >> 12;
+	inst_pa_page = nvgpu_inst_block_addr(g, &g->mm.hwpm.inst_block) >> 12;
 
 	gk20a_writel(g, perf_pmasys_mem_block_r(),
 			perf_pmasys_mem_block_base_f(inst_pa_page) |

drivers/gpu/nvgpu/gv11b/dbg_gpu_gv11b.c

@@ -58,8 +58,7 @@ int gv11b_perfbuf_enable_locked(struct gk20a *g, u64 offset, u32 size)
 	gk20a_writel(g, perf_pmasys_outsize_r(), size);
 
 	/* this field is aligned to 4K */
-	inst_pa_page = gk20a_mm_inst_block_addr(g,
-			&mm->perfbuf.inst_block) >> 12;
+	inst_pa_page = nvgpu_inst_block_addr(g, &mm->perfbuf.inst_block) >> 12;
 
 	gk20a_writel(g, perf_pmasys_mem_block_r(),
 			perf_pmasys_mem_block_base_f(inst_pa_page) |

drivers/gpu/nvgpu/gv11b/fifo_gv11b.c

@@ -34,6 +34,7 @@
 #include <nvgpu/debug.h>
 #include <nvgpu/nvhost_t19x.h>
 #include <nvgpu/barrier.h>
+#include <nvgpu/mm.h>
 
 #include "gk20a/gk20a.h"
 #include "gk20a/fifo_gk20a.h"
@@ -112,9 +113,9 @@ void gv11b_get_ch_runlist_entry(struct channel_gk20a *c, u32 *runlist)
 	runlist[0] = runlist_entry | ram_rl_entry_chan_userd_ptr_lo_f(addr_lo);
 	runlist[1] = ram_rl_entry_chan_userd_ptr_hi_f(addr_hi);
 
-	addr_lo = u64_lo32(gk20a_mm_inst_block_addr(g, &c->inst_block)) >>
+	addr_lo = u64_lo32(nvgpu_inst_block_addr(g, &c->inst_block)) >>
 			ram_rl_entry_chan_inst_ptr_align_shift_v();
-	addr_hi = u64_hi32(gk20a_mm_inst_block_addr(g, &c->inst_block));
+	addr_hi = u64_hi32(nvgpu_inst_block_addr(g, &c->inst_block));
 
 	runlist[2] = ram_rl_entry_chan_inst_ptr_lo_f(addr_lo) |
 				ram_rl_entry_chid_f(c->chid);

drivers/gpu/nvgpu/gv11b/hal_gv11b.c

@@ -549,6 +549,7 @@ static const struct gpu_ops gv11b_ops = {
 		.init_pdb = gp10b_mm_init_pdb,
 		.init_mm_setup_hw = gv11b_init_mm_setup_hw,
 		.is_bar1_supported = gv11b_mm_is_bar1_supported,
+		.alloc_inst_block = gk20a_alloc_inst_block,
 		.init_inst_block = gv11b_init_inst_block,
 		.mmu_fault_pending = gv11b_mm_mmu_fault_pending,
 		.get_kind_invalid = gm20b_get_kind_invalid,

drivers/gpu/nvgpu/gv11b/mm_gv11b.c

@@ -27,6 +27,7 @@
 #include <nvgpu/kmem.h>
 #include <nvgpu/dma.h>
 #include <nvgpu/log.h>
+#include <nvgpu/mm.h>
 
 #include "gk20a/gk20a.h"
 #include "gk20a/mm_gk20a.h"
@@ -54,7 +55,7 @@ void gv11b_init_inst_block(struct nvgpu_mem *inst_block,
 	struct gk20a *g = gk20a_from_vm(vm);
 
 	gk20a_dbg_info("inst block phys = 0x%llx, kv = 0x%p",
-		gk20a_mm_inst_block_addr(g, inst_block), inst_block->cpu_va);
+		nvgpu_inst_block_addr(g, inst_block), inst_block->cpu_va);
 
 	g->ops.mm.init_pdb(g, inst_block, vm);
 
@@ -191,7 +192,7 @@ void gv11b_mm_remove_bar2_vm(struct gk20a *g)
 
 	gv11b_mm_mmu_hw_fault_buf_deinit(g);
 
-	gk20a_free_inst_block(g, &mm->bar2.inst_block);
+	nvgpu_free_inst_block(g, &mm->bar2.inst_block);
 	nvgpu_vm_put(mm->bar2.vm);
 }
 
@@ -282,7 +283,7 @@ int gv11b_init_bar2_mm_hw_setup(struct gk20a *g)
 {
 	struct mm_gk20a *mm = &g->mm;
 	struct nvgpu_mem *inst_block = &mm->bar2.inst_block;
-	u64 inst_pa = gk20a_mm_inst_block_addr(g, inst_block);
+	u64 inst_pa = nvgpu_inst_block_addr(g, inst_block);
 	u32 reg_val;
 	struct nvgpu_timeout timeout;
 	u32 delay = GR_IDLE_CHECK_DEFAULT;

drivers/gpu/nvgpu/gv11b/pmu_gv11b.c

@@ -30,6 +30,7 @@
 #include <nvgpu/pmu.h>
 #include <nvgpu/falcon.h>
 #include <nvgpu/enabled.h>
+#include <nvgpu/mm.h>
 
 #include "gk20a/gk20a.h"
 
@@ -104,7 +105,7 @@ int gv11b_pmu_bootstrap(struct nvgpu_pmu *pmu)
 
 	gk20a_writel(g, pwr_pmu_new_instblk_r(),
 		pwr_pmu_new_instblk_ptr_f(
-		gk20a_mm_inst_block_addr(g, &mm->pmu.inst_block) >> ALIGN_4KB)
+		nvgpu_inst_block_addr(g, &mm->pmu.inst_block) >> ALIGN_4KB)
 		| pwr_pmu_new_instblk_valid_f(1)
 		| pwr_pmu_new_instblk_target_sys_ncoh_f());