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gpu: nvgpu: gv11b: header updates for CL#37119043

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Bug 1735760

Change-Id: I5216863a25338f14498ae0be58b86993104d4e99
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: http://git-master/r/1222031
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Seema Khowala
2016-09-22 14:41:31 -07:00
committed by mobile promotions
parent 8fdf40a849
commit 09168aac40
6 changed files with 290 additions and 529 deletions
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205
drivers/gpu/nvgpu/gv11b/gr_gv11b.c
View File

@@ -67,105 +67,16 @@ static int gr_gv11b_handle_sm_exception(struct gk20a *g, u32 gpc, u32 tpc,
int ret = 0;
u32 offset = proj_gpc_stride_v() * gpc +
proj_tpc_in_gpc_stride_v() * tpc;
u32 lrf_ecc_status, shm_ecc_status;
u32 lrf_ecc_status;
gr_gk20a_handle_sm_exception(g, gpc, tpc, post_event, fault_ch, hww_global_esr);
/* Check for LRF ECC errors. */
lrf_ecc_status = gk20a_readl(g,
gr_pri_gpc0_tpc0_sm_lrf_ecc_status_r() + offset);
if ((lrf_ecc_status &
gr_pri_gpc0_tpc0_sm_lrf_ecc_status_single_err_detected_qrfdp0_pending_f()) ||
(lrf_ecc_status &
gr_pri_gpc0_tpc0_sm_lrf_ecc_status_single_err_detected_qrfdp1_pending_f()) ||
(lrf_ecc_status &
gr_pri_gpc0_tpc0_sm_lrf_ecc_status_single_err_detected_qrfdp2_pending_f()) ||
(lrf_ecc_status &
gr_pri_gpc0_tpc0_sm_lrf_ecc_status_single_err_detected_qrfdp3_pending_f())) {
gk20a_dbg(gpu_dbg_fn | gpu_dbg_intr,
"Single bit error detected in SM LRF!");
g->gr.t18x.ecc_stats.sm_lrf_single_err_count.counters[tpc] +=
gk20a_readl(g,
gr_pri_gpc0_tpc0_sm_lrf_ecc_single_err_count_r() + offset);
gk20a_writel(g,
gr_pri_gpc0_tpc0_sm_lrf_ecc_single_err_count_r() + offset,
0);
}
if ((lrf_ecc_status &
gr_pri_gpc0_tpc0_sm_lrf_ecc_status_double_err_detected_qrfdp0_pending_f()) ||
(lrf_ecc_status &
gr_pri_gpc0_tpc0_sm_lrf_ecc_status_double_err_detected_qrfdp1_pending_f()) ||
(lrf_ecc_status &
gr_pri_gpc0_tpc0_sm_lrf_ecc_status_double_err_detected_qrfdp2_pending_f()) ||
(lrf_ecc_status &
gr_pri_gpc0_tpc0_sm_lrf_ecc_status_double_err_detected_qrfdp3_pending_f())) {
gk20a_dbg(gpu_dbg_fn | gpu_dbg_intr,
"Double bit error detected in SM LRF!");
g->gr.t18x.ecc_stats.sm_lrf_double_err_count.counters[tpc] +=
gk20a_readl(g,
gr_pri_gpc0_tpc0_sm_lrf_ecc_double_err_count_r() + offset);
gk20a_writel(g,
gr_pri_gpc0_tpc0_sm_lrf_ecc_double_err_count_r() + offset, 0);
}
gk20a_writel(g, gr_pri_gpc0_tpc0_sm_lrf_ecc_status_r() + offset,
lrf_ecc_status);
/* Check for SHM ECC errors. */
shm_ecc_status = gk20a_readl(g,
gr_pri_gpc0_tpc0_sm_shm_ecc_status_r() + offset);
if ((shm_ecc_status &
gr_pri_gpc0_tpc0_sm_shm_ecc_status_single_err_corrected_shm0_pending_f()) ||
(shm_ecc_status &
gr_pri_gpc0_tpc0_sm_shm_ecc_status_single_err_corrected_shm1_pending_f()) ||
(shm_ecc_status &
gr_pri_gpc0_tpc0_sm_shm_ecc_status_single_err_detected_shm0_pending_f()) ||
(shm_ecc_status &
gr_pri_gpc0_tpc0_sm_shm_ecc_status_single_err_detected_shm1_pending_f())) {
u32 ecc_stats_reg_val;
gk20a_dbg(gpu_dbg_fn | gpu_dbg_intr,
"Single bit error detected in SM SHM!");
ecc_stats_reg_val =
gk20a_readl(g,
gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_r() + offset);
g->gr.t18x.ecc_stats.sm_shm_sec_count.counters[tpc] +=
gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_corrected_v(ecc_stats_reg_val);
g->gr.t18x.ecc_stats.sm_shm_sed_count.counters[tpc] +=
gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_detected_v(ecc_stats_reg_val);
ecc_stats_reg_val &= ~(gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_corrected_m() |
gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_detected_m());
gk20a_writel(g,
gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_r() + offset,
ecc_stats_reg_val);
}
if ((shm_ecc_status &
gr_pri_gpc0_tpc0_sm_shm_ecc_status_double_err_detected_shm0_pending_f()) ||
(shm_ecc_status &
gr_pri_gpc0_tpc0_sm_shm_ecc_status_double_err_detected_shm1_pending_f())) {
u32 ecc_stats_reg_val;
gk20a_dbg(gpu_dbg_fn | gpu_dbg_intr,
"Double bit error detected in SM SHM!");
ecc_stats_reg_val =
gk20a_readl(g,
gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_r() + offset);
g->gr.t18x.ecc_stats.sm_shm_ded_count.counters[tpc] +=
gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_double_detected_v(ecc_stats_reg_val);
ecc_stats_reg_val &= ~(gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_double_detected_m());
gk20a_writel(g,
gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_r() + offset,
ecc_stats_reg_val);
}
gk20a_writel(g, gr_pri_gpc0_tpc0_sm_shm_ecc_status_r() + offset,
shm_ecc_status);
return ret;
}
@@ -176,7 +87,6 @@ static int gr_gv11b_handle_tex_exception(struct gk20a *g, u32 gpc, u32 tpc,
u32 offset = proj_gpc_stride_v() * gpc +
proj_tpc_in_gpc_stride_v() * tpc;
u32 esr;
u32 ecc_stats_reg_val;
gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, "");
@@ -184,119 +94,6 @@ static int gr_gv11b_handle_tex_exception(struct gk20a *g, u32 gpc, u32 tpc,
gr_gpc0_tpc0_tex_m_hww_esr_r() + offset);
gk20a_dbg(gpu_dbg_intr | gpu_dbg_gpu_dbg, "0x%08x", esr);
if (esr & gr_gpc0_tpc0_tex_m_hww_esr_ecc_sec_pending_f()) {
gk20a_dbg(gpu_dbg_fn | gpu_dbg_intr,
"Single bit error detected in TEX!");
/* Pipe 0 counters */
gk20a_writel(g,
gr_pri_gpc0_tpc0_tex_m_routing_r() + offset,
gr_pri_gpc0_tpc0_tex_m_routing_sel_pipe0_f());
ecc_stats_reg_val = gk20a_readl(g,
gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_r() + offset);
g->gr.t18x.ecc_stats.tex_total_sec_pipe0_count.counters[tpc] +=
gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_sec_v(ecc_stats_reg_val);
ecc_stats_reg_val &= ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_sec_m();
gk20a_writel(g,
gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_r() + offset,
ecc_stats_reg_val);
ecc_stats_reg_val = gk20a_readl(g,
gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_r() + offset);
g->gr.t18x.ecc_stats.tex_unique_sec_pipe0_count.counters[tpc] +=
gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_sec_v(ecc_stats_reg_val);
ecc_stats_reg_val &= ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_sec_m();
gk20a_writel(g,
gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_r() + offset,
ecc_stats_reg_val);
/* Pipe 1 counters */
gk20a_writel(g,
gr_pri_gpc0_tpc0_tex_m_routing_r() + offset,
gr_pri_gpc0_tpc0_tex_m_routing_sel_pipe1_f());
ecc_stats_reg_val = gk20a_readl(g,
gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_r() + offset);
g->gr.t18x.ecc_stats.tex_total_sec_pipe1_count.counters[tpc] +=
gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_sec_v(ecc_stats_reg_val);
ecc_stats_reg_val &= ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_sec_m();
gk20a_writel(g,
gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_r() + offset,
ecc_stats_reg_val);
ecc_stats_reg_val = gk20a_readl(g,
gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_r() + offset);
g->gr.t18x.ecc_stats.tex_unique_sec_pipe1_count.counters[tpc] +=
gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_sec_v(ecc_stats_reg_val);
ecc_stats_reg_val &= ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_sec_m();
gk20a_writel(g,
gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_r() + offset,
ecc_stats_reg_val);
gk20a_writel(g,
gr_pri_gpc0_tpc0_tex_m_routing_r() + offset,
gr_pri_gpc0_tpc0_tex_m_routing_sel_default_f());
}
if (esr & gr_gpc0_tpc0_tex_m_hww_esr_ecc_ded_pending_f()) {
gk20a_dbg(gpu_dbg_fn | gpu_dbg_intr,
"Double bit error detected in TEX!");
/* Pipe 0 counters */
gk20a_writel(g,
gr_pri_gpc0_tpc0_tex_m_routing_r() + offset,
gr_pri_gpc0_tpc0_tex_m_routing_sel_pipe0_f());
ecc_stats_reg_val = gk20a_readl(g,
gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_r() + offset);
g->gr.t18x.ecc_stats.tex_total_ded_pipe0_count.counters[tpc] +=
gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_ded_v(ecc_stats_reg_val);
ecc_stats_reg_val &= ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_ded_m();
gk20a_writel(g,
gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_r() + offset,
ecc_stats_reg_val);
ecc_stats_reg_val = gk20a_readl(g,
gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_r() + offset);
g->gr.t18x.ecc_stats.tex_unique_ded_pipe0_count.counters[tpc] +=
gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_ded_v(ecc_stats_reg_val);
ecc_stats_reg_val &= ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_ded_m();
gk20a_writel(g,
gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_r() + offset,
ecc_stats_reg_val);
/* Pipe 1 counters */
gk20a_writel(g,
gr_pri_gpc0_tpc0_tex_m_routing_r() + offset,
gr_pri_gpc0_tpc0_tex_m_routing_sel_pipe1_f());
ecc_stats_reg_val = gk20a_readl(g,
gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_r() + offset);
g->gr.t18x.ecc_stats.tex_total_ded_pipe1_count.counters[tpc] +=
gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_ded_v(ecc_stats_reg_val);
ecc_stats_reg_val &= ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_ded_m();
gk20a_writel(g,
gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_r() + offset,
ecc_stats_reg_val);
ecc_stats_reg_val = gk20a_readl(g,
gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_r() + offset);
g->gr.t18x.ecc_stats.tex_unique_ded_pipe1_count.counters[tpc] +=
gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_ded_v(ecc_stats_reg_val);
ecc_stats_reg_val &= ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_ded_m();
gk20a_writel(g,
gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_r() + offset,
ecc_stats_reg_val);
gk20a_writel(g,
gr_pri_gpc0_tpc0_tex_m_routing_r() + offset,
gr_pri_gpc0_tpc0_tex_m_routing_sel_default_f());
}
gk20a_writel(g,
gr_gpc0_tpc0_tex_m_hww_esr_r() + offset,
esr);

88
drivers/gpu/nvgpu/gv11b/hw_fifo_gv11b.h
View File

@@ -190,22 +190,6 @@ static inline u32 fifo_intr_0_lb_error_reset_f(void)
{
return 0x1000000;
}
static inline u32 fifo_intr_0_replayable_fault_error_pending_f(void)
{
return 0x2000000;
}
static inline u32 fifo_intr_0_dropped_mmu_fault_pending_f(void)
{
return 0x8000000;
}
static inline u32 fifo_intr_0_dropped_mmu_fault_reset_f(void)
{
return 0x8000000;
}
static inline u32 fifo_intr_0_mmu_fault_pending_f(void)
{
return 0x10000000;
}
static inline u32 fifo_intr_0_pbdma_intr_pending_f(void)
{
return 0x20000000;
@@ -230,14 +214,6 @@ static inline u32 fifo_intr_en_0_sched_error_m(void)
{
return 0x1 << 8;
}
static inline u32 fifo_intr_en_0_mmu_fault_f(u32 v)
{
return (v & 0x1) << 28;
}
static inline u32 fifo_intr_en_0_mmu_fault_m(void)
{
return 0x1 << 28;
}
static inline u32 fifo_intr_en_1_r(void)
{
return 0x00002528;
@@ -262,62 +238,14 @@ static inline u32 fifo_intr_chsw_error_r(void)
{
return 0x0000256c;
}
static inline u32 fifo_intr_mmu_fault_id_r(void)
{
return 0x0000259c;
}
static inline u32 fifo_intr_mmu_fault_eng_id_graphics_v(void)
{
return 0x00000040;
}
static inline u32 fifo_intr_mmu_fault_eng_id_graphics_f(void)
{
return 0x0;
}
static inline u32 fifo_intr_mmu_fault_inst_r(u32 i)
{
return 0x00002800 + i*16;
}
static inline u32 fifo_intr_mmu_fault_inst_ptr_v(u32 r)
{
return (r >> 0) & 0xfffffff;
}
static inline u32 fifo_intr_mmu_fault_inst_ptr_align_shift_v(void)
{
return 0x0000000c;
}
static inline u32 fifo_intr_mmu_fault_lo_r(u32 i)
{
return 0x00002804 + i*16;
}
static inline u32 fifo_intr_mmu_fault_hi_r(u32 i)
{
return 0x00002808 + i*16;
}
static inline u32 fifo_intr_mmu_fault_info_r(u32 i)
{
return 0x0000280c + i*16;
}
static inline u32 fifo_intr_mmu_fault_info_type_v(u32 r)
{
return (r >> 0) & 0x1f;
}
static inline u32 fifo_intr_mmu_fault_info_client_type_v(u32 r)
{
return (r >> 20) & 0x1;
}
static inline u32 fifo_intr_mmu_fault_info_client_type_gpc_v(void)
static inline u32 fifo_gpc_v(void)
{
return 0x00000000;
}
static inline u32 fifo_intr_mmu_fault_info_client_type_hub_v(void)
static inline u32 fifo_hub_v(void)
{
return 0x00000001;
}
static inline u32 fifo_intr_mmu_fault_info_client_v(u32 r)
{
return (r >> 8) & 0x7f;
}
static inline u32 fifo_intr_pbdma_id_r(void)
{
return 0x000025a0;
@@ -394,18 +322,6 @@ static inline u32 fifo_preempt_id_f(u32 v)
{
return (v & 0xfff) << 0;
}
static inline u32 fifo_trigger_mmu_fault_r(u32 i)
{
return 0x00002a30 + i*4;
}
static inline u32 fifo_trigger_mmu_fault_id_f(u32 v)
{
return (v & 0x1f) << 0;
}
static inline u32 fifo_trigger_mmu_fault_enable_f(u32 v)
{
return (v & 0x1) << 8;
}
static inline u32 fifo_engine_status_r(u32 i)
{
return 0x00002640 + i*8;

174
drivers/gpu/nvgpu/gv11b/hw_gr_gv11b.h
View File

@@ -470,102 +470,6 @@ static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_r(void)
{
return 0x00504358;
}
static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_single_err_detected_qrfdp0_pending_f(void)
{
return 0x10;
}
static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_single_err_detected_qrfdp1_pending_f(void)
{
return 0x20;
}
static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_single_err_detected_qrfdp2_pending_f(void)
{
return 0x40;
}
static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_single_err_detected_qrfdp3_pending_f(void)
{
return 0x80;
}
static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_double_err_detected_qrfdp0_pending_f(void)
{
return 0x100;
}
static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_double_err_detected_qrfdp1_pending_f(void)
{
return 0x200;
}
static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_double_err_detected_qrfdp2_pending_f(void)
{
return 0x400;
}
static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_double_err_detected_qrfdp3_pending_f(void)
{
return 0x800;
}
static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_status_r(void)
{
return 0x0050436c;
}
static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_status_single_err_corrected_shm0_pending_f(void)
{
return 0x1;
}
static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_status_single_err_corrected_shm1_pending_f(void)
{
return 0x2;
}
static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_status_single_err_detected_shm0_pending_f(void)
{
return 0x10;
}
static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_status_single_err_detected_shm1_pending_f(void)
{
return 0x20;
}
static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_status_double_err_detected_shm0_pending_f(void)
{
return 0x100;
}
static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_status_double_err_detected_shm1_pending_f(void)
{
return 0x200;
}
static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_single_err_count_r(void)
{
return 0x0050435c;
}
static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_double_err_count_r(void)
{
return 0x00504360;
}
static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_r(void)
{
return 0x00504370;
}
static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_corrected_m(void)
{
return 0xff << 0;
}
static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_corrected_v(u32 r)
{
return (r >> 0) & 0xff;
}
static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_detected_m(void)
{
return 0xff << 8;
}
static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_detected_v(u32 r)
{
return (r >> 8) & 0xff;
}
static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_double_detected_m(void)
{
return 0xff << 16;
}
static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_double_detected_v(u32 r)
{
return (r >> 16) & 0xff;
}
static inline u32 gr_pri_gpc0_tpc0_tex_m_routing_r(void)
{
return 0x005042c4;
@@ -582,46 +486,6 @@ static inline u32 gr_pri_gpc0_tpc0_tex_m_routing_sel_pipe1_f(void)
{
return 0x2;
}
static inline u32 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_r(void)
{
return 0x00504218;
}
static inline u32 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_sec_m(void)
{
return 0xffff << 0;
}
static inline u32 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_sec_v(u32 r)
{
return (r >> 0) & 0xffff;
}
static inline u32 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_ded_m(void)
{
return 0xffff << 16;
}
static inline u32 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_ded_v(u32 r)
{
return (r >> 16) & 0xffff;
}
static inline u32 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_r(void)
{
return 0x005042ec;
}
static inline u32 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_sec_m(void)
{
return 0xffff << 0;
}
static inline u32 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_sec_v(u32 r)
{
return (r >> 0) & 0xffff;
}
static inline u32 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_ded_m(void)
{
return 0xffff << 16;
}
static inline u32 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_ded_v(u32 r)
{
return (r >> 16) & 0xffff;
}
static inline u32 gr_pri_be0_crop_status1_r(void)
{
return 0x00410134;
@@ -654,6 +518,14 @@ static inline u32 gr_pipe_bundle_address_value_v(u32 r)
{
return (r >> 0) & 0xffff;
}
static inline u32 gr_pipe_bundle_address_veid_f(u32 v)
{
return (v & 0x3f) << 20;
}
static inline u32 gr_pipe_bundle_address_veid_v(u32 r)
{
return (r >> 20) & 0x3f;
}
static inline u32 gr_pipe_bundle_data_r(void)
{
return 0x00400204;
@@ -1498,14 +1370,6 @@ static inline u32 gr_fecs_feature_override_ecc_sm_lrf_override_v(u32 r)
{
return (r >> 3) & 0x1;
}
static inline u32 gr_fecs_feature_override_ecc_sm_shm_override_v(u32 r)
{
return (r >> 7) & 0x1;
}
static inline u32 gr_fecs_feature_override_ecc_tex_override_v(u32 r)
{
return (r >> 11) & 0x1;
}
static inline u32 gr_fecs_feature_override_ecc_ltc_override_v(u32 r)
{
return (r >> 15) & 0x1;
@@ -1514,14 +1378,6 @@ static inline u32 gr_fecs_feature_override_ecc_sm_lrf_v(u32 r)
{
return (r >> 0) & 0x1;
}
static inline u32 gr_fecs_feature_override_ecc_sm_shm_v(u32 r)
{
return (r >> 4) & 0x1;
}
static inline u32 gr_fecs_feature_override_ecc_tex_v(u32 r)
{
return (r >> 8) & 0x1;
}
static inline u32 gr_fecs_feature_override_ecc_ltc_v(u32 r)
{
return (r >> 12) & 0x1;
@@ -2384,11 +2240,11 @@ static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_m(void)
}
static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_default_v(void)
{
return 0x00001000;
return 0x00000800;
}
static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_gfxp_v(void)
{
return 0x00001900;
return 0x00001100;
}
static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_granularity_v(void)
{
@@ -2432,7 +2288,7 @@ static inline u32 gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_v_f(u32 v)
}
static inline u32 gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_v_default_v(void)
{
return 0x00001000;
return 0x00000800;
}
static inline u32 gr_gpcs_tpcs_tex_rm_cb_0_r(void)
{
@@ -3266,14 +3122,6 @@ static inline u32 gr_gpc0_tpc0_tex_m_hww_esr_intr_pending_f(void)
{
return 0x1;
}
static inline u32 gr_gpc0_tpc0_tex_m_hww_esr_ecc_sec_pending_f(void)
{
return 0x80;
}
static inline u32 gr_gpc0_tpc0_tex_m_hww_esr_ecc_ded_pending_f(void)
{
return 0x100;
}
static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_r(void)
{
return 0x00504730;

16
drivers/gpu/nvgpu/gv11b/hw_pbdma_gv11b.h
View File

@@ -574,4 +574,20 @@ static inline u32 pbdma_runlist_timeslice_enable_true_f(void)
{
return 0x10000000;
}
static inline u32 pbdma_set_channel_info_r(u32 i)
{
return 0x000400fc + i*8192;
}
static inline u32 pbdma_set_channel_info_scg_type_graphics_compute0_f(void)
{
return 0x0;
}
static inline u32 pbdma_set_channel_info_scg_type_compute1_f(void)
{
return 0x1;
}
static inline u32 pbdma_set_channel_info_veid_f(u32 v)
{
return (v & 0x3f) << 8;
}
#endif

8
drivers/gpu/nvgpu/gv11b/hw_proj_gv11b.h
View File

@@ -114,17 +114,21 @@ static inline u32 proj_host_num_pbdma_v(void)
{
return 0x00000003;
}
static inline u32 proj_litter_num_subctx_v(void)
{
return 0x00000040;
}
static inline u32 proj_scal_litter_num_tpc_per_gpc_v(void)
{
return 0x00000004;
}
static inline u32 proj_scal_litter_num_fbps_v(void)
{
return 0x00000002;
return 0x00000001;
}
static inline u32 proj_scal_litter_num_fbpas_v(void)
{
return 0x00000004;
return 0x00000002;
}
static inline u32 proj_scal_litter_num_gpcs_v(void)
{

328
drivers/gpu/nvgpu/gv11b/hw_ram_gv11b.h
View File

@@ -86,37 +86,9 @@ static inline u32 ram_in_page_dir_base_vol_true_f(void)
{
return 0x4;
}
static inline u32 ram_in_page_dir_base_fault_replay_tex_f(u32 v)
static inline u32 ram_in_page_dir_base_vol_false_f(void)
{
return (v & 0x1) << 4;
}
static inline u32 ram_in_page_dir_base_fault_replay_tex_m(void)
{
return 0x1 << 4;
}
static inline u32 ram_in_page_dir_base_fault_replay_tex_w(void)
{
return 128;
}
static inline u32 ram_in_page_dir_base_fault_replay_tex_true_f(void)
{
return 0x10;
}
static inline u32 ram_in_page_dir_base_fault_replay_gcc_f(u32 v)
{
return (v & 0x1) << 5;
}
static inline u32 ram_in_page_dir_base_fault_replay_gcc_m(void)
{
return 0x1 << 5;
}
static inline u32 ram_in_page_dir_base_fault_replay_gcc_w(void)
{
return 128;
}
static inline u32 ram_in_page_dir_base_fault_replay_gcc_true_f(void)
{
return 0x20;
return 0x0;
}
static inline u32 ram_in_big_page_size_f(u32 v)
{
@@ -154,22 +126,6 @@ static inline u32 ram_in_page_dir_base_hi_w(void)
{
return 129;
}
static inline u32 ram_in_adr_limit_lo_f(u32 v)
{
return (v & 0xfffff) << 12;
}
static inline u32 ram_in_adr_limit_lo_w(void)
{
return 130;
}
static inline u32 ram_in_adr_limit_hi_f(u32 v)
{
return (v & 0xffffffff) << 0;
}
static inline u32 ram_in_adr_limit_hi_w(void)
{
return 131;
}
static inline u32 ram_in_engine_cs_w(void)
{
return 132;
@@ -190,54 +146,274 @@ static inline u32 ram_in_engine_cs_fg_f(void)
{
return 0x8;
}
static inline u32 ram_in_gr_cs_w(void)
static inline u32 ram_in_engine_wfi_mode_w(void)
{
return 132;
}
static inline u32 ram_in_gr_cs_wfi_f(void)
{
return 0x0;
}
static inline u32 ram_in_gr_wfi_target_w(void)
{
return 132;
}
static inline u32 ram_in_gr_wfi_mode_w(void)
{
return 132;
}
static inline u32 ram_in_gr_wfi_mode_physical_v(void)
static inline u32 ram_in_engine_wfi_mode_physical_v(void)
{
return 0x00000000;
}
static inline u32 ram_in_gr_wfi_mode_physical_f(void)
static inline u32 ram_in_engine_wfi_mode_physical_f(void)
{
return 0x0;
}
static inline u32 ram_in_gr_wfi_mode_virtual_v(void)
static inline u32 ram_in_engine_wfi_mode_virtual_v(void)
{
return 0x00000001;
}
static inline u32 ram_in_gr_wfi_mode_virtual_f(void)
static inline u32 ram_in_engine_wfi_mode_virtual_f(void)
{
return 0x4;
}
static inline u32 ram_in_gr_wfi_ptr_lo_f(u32 v)
{
return (v & 0xfffff) << 12;
}
static inline u32 ram_in_gr_wfi_ptr_lo_w(void)
static inline u32 ram_in_engine_wfi_target_w(void)
{
return 132;
}
static inline u32 ram_in_gr_wfi_ptr_hi_f(u32 v)
static inline u32 ram_in_engine_wfi_target_sys_mem_coh_v(void)
{
return 0x00000002;
}
static inline u32 ram_in_engine_wfi_target_sys_mem_coh_f(void)
{
return 0x2;
}
static inline u32 ram_in_engine_wfi_target_sys_mem_nocoh_v(void)
{
return 0x00000003;
}
static inline u32 ram_in_engine_wfi_target_sys_mem_nocoh_f(void)
{
return 0x3;
}
static inline u32 ram_in_engine_wfi_target_local_mem_v(void)
{
return 0x00000000;
}
static inline u32 ram_in_engine_wfi_target_local_mem_f(void)
{
return 0x0;
}
static inline u32 ram_in_engine_wfi_ptr_lo_f(u32 v)
{
return (v & 0xfffff) << 12;
}
static inline u32 ram_in_engine_wfi_ptr_lo_w(void)
{
return 132;
}
static inline u32 ram_in_engine_wfi_ptr_hi_f(u32 v)
{
return (v & 0xff) << 0;
}
static inline u32 ram_in_gr_wfi_ptr_hi_w(void)
static inline u32 ram_in_engine_wfi_ptr_hi_w(void)
{
return 133;
}
static inline u32 ram_in_engine_wfi_veid_f(u32 v)
{
return (v & 0x3f) << 0;
}
static inline u32 ram_in_engine_wfi_veid_w(void)
{
return 134;
}
static inline u32 ram_in_eng_method_buffer_addr_lo_f(u32 v)
{
return (v & 0xffffffff) << 0;
}
static inline u32 ram_in_eng_method_buffer_addr_lo_w(void)
{
return 136;
}
static inline u32 ram_in_eng_method_buffer_addr_hi_f(u32 v)
{
return (v & 0x1ffff) << 0;
}
static inline u32 ram_in_eng_method_buffer_addr_hi_w(void)
{
return 137;
}
static inline u32 ram_in_sc_page_dir_base_target_f(u32 v, u32 i)
{
return (v & 0x3) << (0 + i*0);
}
static inline u32 ram_in_sc_page_dir_base_target__size_1_v(void)
{
return 0x00000040;
}
static inline u32 ram_in_sc_page_dir_base_target_vid_mem_v(void)
{
return 0x00000000;
}
static inline u32 ram_in_sc_page_dir_base_target_invalid_v(void)
{
return 0x00000001;
}
static inline u32 ram_in_sc_page_dir_base_target_sys_mem_coh_v(void)
{
return 0x00000002;
}
static inline u32 ram_in_sc_page_dir_base_target_sys_mem_ncoh_v(void)
{
return 0x00000003;
}
static inline u32 ram_in_sc_page_dir_base_vol_f(u32 v, u32 i)
{
return (v & 0x1) << (2 + i*0);
}
static inline u32 ram_in_sc_page_dir_base_vol__size_1_v(void)
{
return 0x00000040;
}
static inline u32 ram_in_sc_page_dir_base_vol_true_v(void)
{
return 0x00000001;
}
static inline u32 ram_in_sc_page_dir_base_vol_false_v(void)
{
return 0x00000000;
}
static inline u32 ram_in_sc_page_dir_base_fault_replay_tex_f(u32 v, u32 i)
{
return (v & 0x1) << (4 + i*0);
}
static inline u32 ram_in_sc_page_dir_base_fault_replay_tex__size_1_v(void)
{
return 0x00000040;
}
static inline u32 ram_in_sc_page_dir_base_fault_replay_tex_enabled_v(void)
{
return 0x00000001;
}
static inline u32 ram_in_sc_page_dir_base_fault_replay_tex_disabled_v(void)
{
return 0x00000000;
}
static inline u32 ram_in_sc_page_dir_base_fault_replay_gcc_f(u32 v, u32 i)
{
return (v & 0x1) << (5 + i*0);
}
static inline u32 ram_in_sc_page_dir_base_fault_replay_gcc__size_1_v(void)
{
return 0x00000040;
}
static inline u32 ram_in_sc_page_dir_base_fault_replay_gcc_enabled_v(void)
{
return 0x00000001;
}
static inline u32 ram_in_sc_page_dir_base_fault_replay_gcc_disabled_v(void)
{
return 0x00000000;
}
static inline u32 ram_in_sc_use_ver2_pt_format_f(u32 v, u32 i)
{
return (v & 0x1) << (10 + i*0);
}
static inline u32 ram_in_sc_use_ver2_pt_format__size_1_v(void)
{
return 0x00000040;
}
static inline u32 ram_in_sc_use_ver2_pt_format_false_v(void)
{
return 0x00000000;
}
static inline u32 ram_in_sc_use_ver2_pt_format_true_v(void)
{
return 0x00000001;
}
static inline u32 ram_in_sc_big_page_size_f(u32 v, u32 i)
{
return (v & 0x1) << (11 + i*0);
}
static inline u32 ram_in_sc_big_page_size__size_1_v(void)
{
return 0x00000040;
}
static inline u32 ram_in_sc_big_page_size_64kb_v(void)
{
return 0x00000001;
}
static inline u32 ram_in_sc_page_dir_base_lo_f(u32 v, u32 i)
{
return (v & 0xfffff) << (12 + i*0);
}
static inline u32 ram_in_sc_page_dir_base_lo__size_1_v(void)
{
return 0x00000040;
}
static inline u32 ram_in_sc_page_dir_base_hi_f(u32 v, u32 i)
{
return (v & 0xffffffff) << (0 + i*0);
}
static inline u32 ram_in_sc_page_dir_base_hi__size_1_v(void)
{
return 0x00000040;
}
static inline u32 ram_in_sc_page_dir_base_target_0_f(u32 v)
{
return (v & 0x3) << 0;
}
static inline u32 ram_in_sc_page_dir_base_target_0_w(void)
{
return 168;
}
static inline u32 ram_in_sc_page_dir_base_vol_0_f(u32 v)
{
return (v & 0x1) << 2;
}
static inline u32 ram_in_sc_page_dir_base_vol_0_w(void)
{
return 168;
}
static inline u32 ram_in_sc_page_dir_base_fault_replay_tex_0_f(u32 v)
{
return (v & 0x1) << 4;
}
static inline u32 ram_in_sc_page_dir_base_fault_replay_tex_0_w(void)
{
return 168;
}
static inline u32 ram_in_sc_page_dir_base_fault_replay_gcc_0_f(u32 v)
{
return (v & 0x1) << 5;
}
static inline u32 ram_in_sc_page_dir_base_fault_replay_gcc_0_w(void)
{
return 168;
}
static inline u32 ram_in_sc_use_ver2_pt_format_0_f(u32 v)
{
return (v & 0x1) << 10;
}
static inline u32 ram_in_sc_use_ver2_pt_format_0_w(void)
{
return 168;
}
static inline u32 ram_in_sc_big_page_size_0_f(u32 v)
{
return (v & 0x1) << 11;
}
static inline u32 ram_in_sc_big_page_size_0_w(void)
{
return 168;
}
static inline u32 ram_in_sc_page_dir_base_lo_0_f(u32 v)
{
return (v & 0xfffff) << 12;
}
static inline u32 ram_in_sc_page_dir_base_lo_0_w(void)
{
return 168;
}
static inline u32 ram_in_sc_page_dir_base_hi_0_f(u32 v)
{
return (v & 0xffffffff) << 0;
}
static inline u32 ram_in_sc_page_dir_base_hi_0_w(void)
{
return 169;
}
static inline u32 ram_in_base_shift_v(void)
{
return 0x0000000c;
@@ -378,6 +554,10 @@ static inline u32 ram_fc_runlist_timeslice_w(void)
{
return 62;
}
static inline u32 ram_fc_set_channel_info_w(void)
{
return 63;
}
static inline u32 ram_userd_base_shift_v(void)
{
return 0x00000009;
@@ -550,10 +730,6 @@ static inline u32 ram_rl_entry_tsg_tsgid_f(u32 v)
{
return (v & 0xfff) << 0;
}
static inline u32 ram_rl_entry_chan_inst_ptr_align_shift_v(void)
{
return 0x0000000c;
}
static inline u32 ram_rl_entry_chan_userd_ptr_align_shift_v(void)
{
return 0x00000008;
@@ -562,4 +738,8 @@ static inline u32 ram_rl_entry_chan_userd_align_shift_v(void)
{
return 0x00000008;
}
static inline u32 ram_rl_entry_chan_inst_ptr_align_shift_v(void)
{
return 0x0000000c;
}
#endif