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gpu: nvgpu: gk20a: MISRA 21.2 header guard fixes
MISRA rule 21.2 doesn't allow the use of macro names which start with an underscore. These leading underscores are to be removed from the macro names. This patch will fix such violations in gk20a hw headers by renaming them to follow the convention, 'NVGPU_HEADER-NAME'. JIRA NVGPU-1028 Change-Id: Ib14774860a784bf066dd958ae1056ecc0115be71 Signed-off-by: smadhavan <smadhavan@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1829809 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> Reviewed-by: Konsta Holtta <kholtta@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
@@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2012-2017, NVIDIA CORPORATION. All rights reserved.
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* Copyright (c) 2012-2018, NVIDIA CORPORATION. All rights reserved.
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*
|
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* Permission is hereby granted, free of charge, to any person obtaining a
|
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* copy of this software and associated documentation files (the "Software"),
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@@ -53,8 +53,8 @@
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* comparison with unshifted values appropriate for use in field <y>
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* of register <x>.
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*/
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#ifndef _hw_bus_gk20a_h_
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#define _hw_bus_gk20a_h_
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#ifndef NVGPU_HW_BUS_GK20A_H
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#define NVGPU_HW_BUS_GK20A_H
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static inline u32 bus_bar0_window_r(void)
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{
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@@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2012-2017, NVIDIA CORPORATION. All rights reserved.
|
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* Copyright (c) 2012-2018, NVIDIA CORPORATION. All rights reserved.
|
||||
*
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||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
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@@ -53,8 +53,8 @@
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* comparison with unshifted values appropriate for use in field <y>
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* of register <x>.
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*/
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#ifndef _hw_ccsr_gk20a_h_
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#define _hw_ccsr_gk20a_h_
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#ifndef NVGPU_HW_CCSR_GK20A_H
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#define NVGPU_HW_CCSR_GK20A_H
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static inline u32 ccsr_channel_inst_r(u32 i)
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{
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@@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2015-2017, NVIDIA CORPORATION. All rights reserved.
|
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* Copyright (c) 2015-2018, NVIDIA CORPORATION. All rights reserved.
|
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
|
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* copy of this software and associated documentation files (the "Software"),
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@@ -53,8 +53,8 @@
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* comparison with unshifted values appropriate for use in field <y>
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* of register <x>.
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*/
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#ifndef _hw_ce2_gk20a_h_
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#define _hw_ce2_gk20a_h_
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#ifndef NVGPU_HW_CE2_GK20A_H
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#define NVGPU_HW_CE2_GK20A_H
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static inline u32 ce2_intr_status_r(void)
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{
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@@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2012-2017, NVIDIA CORPORATION. All rights reserved.
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* Copyright (c) 2012-2018, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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@@ -53,8 +53,8 @@
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* comparison with unshifted values appropriate for use in field <y>
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* of register <x>.
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*/
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#ifndef _hw_ctxsw_prog_gk20a_h_
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#define _hw_ctxsw_prog_gk20a_h_
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#ifndef NVGPU_HW_CTXSW_PROG_GK20A_H
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#define NVGPU_HW_CTXSW_PROG_GK20A_H
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static inline u32 ctxsw_prog_fecs_header_v(void)
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{
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@@ -53,8 +53,8 @@
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* comparison with unshifted values appropriate for use in field <y>
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* of register <x>.
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*/
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#ifndef _hw_falcon_gk20a_h_
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#define _hw_falcon_gk20a_h_
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#ifndef NVGPU_HW_FALCON_GK20A_H
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#define NVGPU_HW_FALCON_GK20A_H
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static inline u32 falcon_falcon_irqsset_r(void)
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{
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@@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2012-2017, NVIDIA CORPORATION. All rights reserved.
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* Copyright (c) 2012-2018, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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@@ -53,8 +53,8 @@
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* comparison with unshifted values appropriate for use in field <y>
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* of register <x>.
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*/
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#ifndef _hw_fb_gk20a_h_
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#define _hw_fb_gk20a_h_
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#ifndef NVGPU_HW_FB_GK20A_H
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#define NVGPU_HW_FB_GK20A_H
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static inline u32 fb_mmu_ctrl_r(void)
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{
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@@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2012-2017, NVIDIA CORPORATION. All rights reserved.
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* Copyright (c) 2012-2018, NVIDIA CORPORATION. All rights reserved.
|
||||
*
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* Permission is hereby granted, free of charge, to any person obtaining a
|
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* copy of this software and associated documentation files (the "Software"),
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@@ -53,8 +53,8 @@
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* comparison with unshifted values appropriate for use in field <y>
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* of register <x>.
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*/
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#ifndef _hw_fifo_gk20a_h_
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#define _hw_fifo_gk20a_h_
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#ifndef NVGPU_HW_FIFO_GK20A_H
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#define NVGPU_HW_FIFO_GK20A_H
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static inline u32 fifo_bar1_base_r(void)
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{
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@@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2012-2017, NVIDIA CORPORATION. All rights reserved.
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* Copyright (c) 2012-2018, NVIDIA CORPORATION. All rights reserved.
|
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
|
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* copy of this software and associated documentation files (the "Software"),
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@@ -53,8 +53,8 @@
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* comparison with unshifted values appropriate for use in field <y>
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* of register <x>.
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*/
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#ifndef _hw_flush_gk20a_h_
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#define _hw_flush_gk20a_h_
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#ifndef NVGPU_HW_FLUSH_GK20A_H
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#define NVGPU_HW_FLUSH_GK20A_H
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static inline u32 flush_l2_system_invalidate_r(void)
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{
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@@ -53,8 +53,8 @@
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* comparison with unshifted values appropriate for use in field <y>
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* of register <x>.
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*/
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#ifndef _hw_gmmu_gk20a_h_
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#define _hw_gmmu_gk20a_h_
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#ifndef NVGPU_HW_GMMU_GK20A_H
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#define NVGPU_HW_GMMU_GK20A_H
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static inline u32 gmmu_pde_aperture_big_w(void)
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{
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@@ -53,8 +53,8 @@
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* comparison with unshifted values appropriate for use in field <y>
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* of register <x>.
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*/
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#ifndef _hw_gr_gk20a_h_
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#define _hw_gr_gk20a_h_
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#ifndef NVGPU_HW_GR_GK20A_H
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#define NVGPU_HW_GR_GK20A_H
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static inline u32 gr_intr_r(void)
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{
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@@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2012-2017, NVIDIA CORPORATION. All rights reserved.
|
||||
* Copyright (c) 2012-2018, NVIDIA CORPORATION. All rights reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
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@@ -53,8 +53,8 @@
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* comparison with unshifted values appropriate for use in field <y>
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* of register <x>.
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*/
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#ifndef _hw_ltc_gk20a_h_
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#define _hw_ltc_gk20a_h_
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#ifndef NVGPU_HW_LTC_GK20A_H
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#define NVGPU_HW_LTC_GK20A_H
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static inline u32 ltc_pltcg_base_v(void)
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{
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@@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2012-2017, NVIDIA CORPORATION. All rights reserved.
|
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* Copyright (c) 2012-2018, NVIDIA CORPORATION. All rights reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
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@@ -53,8 +53,8 @@
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* comparison with unshifted values appropriate for use in field <y>
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* of register <x>.
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*/
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#ifndef _hw_mc_gk20a_h_
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#define _hw_mc_gk20a_h_
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#ifndef NVGPU_HW_MC_GK20A_H
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#define NVGPU_HW_MC_GK20A_H
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static inline u32 mc_boot_0_r(void)
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{
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@@ -53,8 +53,8 @@
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* comparison with unshifted values appropriate for use in field <y>
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* of register <x>.
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*/
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#ifndef _hw_pbdma_gk20a_h_
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#define _hw_pbdma_gk20a_h_
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#ifndef NVGPU_HW_PBDMA_GK20A_H
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#define NVGPU_HW_PBDMA_GK20A_H
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static inline u32 pbdma_gp_entry1_r(void)
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{
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@@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2015-2017, NVIDIA CORPORATION. All rights reserved.
|
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* Copyright (c) 2015-2018, NVIDIA CORPORATION. All rights reserved.
|
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*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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@@ -53,8 +53,8 @@
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* comparison with unshifted values appropriate for use in field <y>
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* of register <x>.
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*/
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#ifndef _hw_perf_gk20a_h_
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#define _hw_perf_gk20a_h_
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#ifndef NVGPU_HW_PERF_GK20A_H
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#define NVGPU_HW_PERF_GK20A_H
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static inline u32 perf_pmasys_control_r(void)
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{
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@@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved.
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* Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
|
||||
*
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* Permission is hereby granted, free of charge, to any person obtaining a
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||||
* copy of this software and associated documentation files (the "Software"),
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@@ -53,8 +53,8 @@
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* comparison with unshifted values appropriate for use in field <y>
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* of register <x>.
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*/
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#ifndef _hw_pram_gk20a_h_
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#define _hw_pram_gk20a_h_
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#ifndef NVGPU_HW_PRAM_GK20A_H
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#define NVGPU_HW_PRAM_GK20A_H
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static inline u32 pram_data032_r(u32 i)
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{
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@@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2012-2017, NVIDIA CORPORATION. All rights reserved.
|
||||
* Copyright (c) 2012-2018, NVIDIA CORPORATION. All rights reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
@@ -53,8 +53,8 @@
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* comparison with unshifted values appropriate for use in field <y>
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* of register <x>.
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*/
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#ifndef _hw_pri_ringmaster_gk20a_h_
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#define _hw_pri_ringmaster_gk20a_h_
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#ifndef NVGPU_HW_PRI_RINGMASTER_GK20A_H
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#define NVGPU_HW_PRI_RINGMASTER_GK20A_H
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static inline u32 pri_ringmaster_command_r(void)
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{
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@@ -1,5 +1,5 @@
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/*
|
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* Copyright (c) 2012-2017, NVIDIA CORPORATION. All rights reserved.
|
||||
* Copyright (c) 2012-2018, NVIDIA CORPORATION. All rights reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
@@ -53,8 +53,8 @@
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* comparison with unshifted values appropriate for use in field <y>
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* of register <x>.
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*/
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#ifndef _hw_pri_ringstation_gpc_gk20a_h_
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#define _hw_pri_ringstation_gpc_gk20a_h_
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#ifndef NVGPU_HW_PRI_RINGSTATION_GPC_GK20A_H
|
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#define NVGPU_HW_PRI_RINGSTATION_GPC_GK20A_H
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static inline u32 pri_ringstation_gpc_master_config_r(u32 i)
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{
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@@ -1,5 +1,5 @@
|
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/*
|
||||
* Copyright (c) 2012-2017, NVIDIA CORPORATION. All rights reserved.
|
||||
* Copyright (c) 2012-2018, NVIDIA CORPORATION. All rights reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
@@ -53,8 +53,8 @@
|
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* comparison with unshifted values appropriate for use in field <y>
|
||||
* of register <x>.
|
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*/
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#ifndef _hw_pri_ringstation_sys_gk20a_h_
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#define _hw_pri_ringstation_sys_gk20a_h_
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#ifndef NVGPU_HW_PRI_RINGSTATION_SYS_GK20A_H
|
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#define NVGPU_HW_PRI_RINGSTATION_SYS_GK20A_H
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|
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static inline u32 pri_ringstation_sys_master_config_r(u32 i)
|
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{
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|
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@@ -53,8 +53,8 @@
|
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* comparison with unshifted values appropriate for use in field <y>
|
||||
* of register <x>.
|
||||
*/
|
||||
#ifndef _hw_proj_gk20a_h_
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#define _hw_proj_gk20a_h_
|
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#ifndef NVGPU_HW_PROJ_GK20A_H
|
||||
#define NVGPU_HW_PROJ_GK20A_H
|
||||
|
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static inline u32 proj_gpc_base_v(void)
|
||||
{
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* Copyright (c) 2012-2017, NVIDIA CORPORATION. All rights reserved.
|
||||
* Copyright (c) 2012-2018, NVIDIA CORPORATION. All rights reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
@@ -53,8 +53,8 @@
|
||||
* comparison with unshifted values appropriate for use in field <y>
|
||||
* of register <x>.
|
||||
*/
|
||||
#ifndef _hw_pwr_gk20a_h_
|
||||
#define _hw_pwr_gk20a_h_
|
||||
#ifndef NVGPU_HW_PWR_GK20A_H
|
||||
#define NVGPU_HW_PWR_GK20A_H
|
||||
|
||||
static inline u32 pwr_falcon_irqsset_r(void)
|
||||
{
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* Copyright (c) 2012-2017, NVIDIA CORPORATION. All rights reserved.
|
||||
* Copyright (c) 2012-2018, NVIDIA CORPORATION. All rights reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
@@ -53,8 +53,8 @@
|
||||
* comparison with unshifted values appropriate for use in field <y>
|
||||
* of register <x>.
|
||||
*/
|
||||
#ifndef _hw_ram_gk20a_h_
|
||||
#define _hw_ram_gk20a_h_
|
||||
#ifndef NVGPU_HW_RAM_GK20A_H
|
||||
#define NVGPU_HW_RAM_GK20A_H
|
||||
|
||||
static inline u32 ram_in_ramfc_s(void)
|
||||
{
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* Copyright (c) 2012-2017, NVIDIA CORPORATION. All rights reserved.
|
||||
* Copyright (c) 2012-2018, NVIDIA CORPORATION. All rights reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
@@ -53,8 +53,8 @@
|
||||
* comparison with unshifted values appropriate for use in field <y>
|
||||
* of register <x>.
|
||||
*/
|
||||
#ifndef _hw_therm_gk20a_h_
|
||||
#define _hw_therm_gk20a_h_
|
||||
#ifndef NVGPU_HW_THERM_GK20A_H
|
||||
#define NVGPU_HW_THERM_GK20A_H
|
||||
|
||||
static inline u32 therm_use_a_r(void)
|
||||
{
|
||||
|
||||
@@ -53,8 +53,8 @@
|
||||
* comparison with unshifted values appropriate for use in field <y>
|
||||
* of register <x>.
|
||||
*/
|
||||
#ifndef _hw_timer_gk20a_h_
|
||||
#define _hw_timer_gk20a_h_
|
||||
#ifndef NVGPU_HW_TIMER_GK20A_H
|
||||
#define NVGPU_HW_TIMER_GK20A_H
|
||||
|
||||
static inline u32 timer_pri_timeout_r(void)
|
||||
{
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* Copyright (c) 2012-2017, NVIDIA CORPORATION. All rights reserved.
|
||||
* Copyright (c) 2012-2018, NVIDIA CORPORATION. All rights reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
@@ -53,8 +53,8 @@
|
||||
* comparison with unshifted values appropriate for use in field <y>
|
||||
* of register <x>.
|
||||
*/
|
||||
#ifndef _hw_top_gk20a_h_
|
||||
#define _hw_top_gk20a_h_
|
||||
#ifndef NVGPU_HW_TOP_GK20A_H
|
||||
#define NVGPU_HW_TOP_GK20A_H
|
||||
|
||||
static inline u32 top_num_gpcs_r(void)
|
||||
{
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* Copyright (c) 2012-2017, NVIDIA CORPORATION. All rights reserved.
|
||||
* Copyright (c) 2012-2018, NVIDIA CORPORATION. All rights reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
@@ -53,8 +53,8 @@
|
||||
* comparison with unshifted values appropriate for use in field <y>
|
||||
* of register <x>.
|
||||
*/
|
||||
#ifndef _hw_trim_gk20a_h_
|
||||
#define _hw_trim_gk20a_h_
|
||||
#ifndef NVGPU_HW_TRIM_GK20A_H
|
||||
#define NVGPU_HW_TRIM_GK20A_H
|
||||
|
||||
static inline u32 trim_sys_gpcpll_cfg_r(void)
|
||||
{
|
||||
|
||||
Reference in New Issue
Block a user