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gpu: nvgpu: remove write to gr_scc_init_r() register

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Register gr_scc_init_r() is deprecated and non-functional since maxwell
Remove write to this register and also remove its accessors

Jira NVGPU-2961

Change-Id: I7ef0c55290003234f795a66435c1f7093827662e
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2072548
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Deepak Nibade
2019-03-13 16:45:38 +05:30
committed by mobile promotions
parent 7fa2189fb3
commit 09e2e8c838
6 changed files with 2 additions and 46 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
drivers/gpu/nvgpu/gk20a/gr_gk20a.c
View File

@@ -1107,10 +1107,6 @@ int gr_gk20a_init_golden_ctx_image(struct gk20a *g,
goto clean_up;
}
/* clear scc ram */
gk20a_writel(g, gr_scc_init_r(),
gr_scc_init_ram_trigger_f());
err = gr_gk20a_fecs_ctx_bind_channel(g, c);
if (err != 0) {
goto clean_up;

10
drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_gr_gm20b.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2014-2019, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -2006,14 +2006,6 @@ static inline u32 gr_scc_pagepool_valid_true_f(void)
{
return 0x80000000U;
}
static inline u32 gr_scc_init_r(void)
{
return 0x0040802cU;
}
static inline u32 gr_scc_init_ram_trigger_f(void)
{
return 0x1U;
}
static inline u32 gr_scc_hww_esr_r(void)
{
return 0x00408030U;

8
drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_gr_gp10b.h
View File

@@ -2222,14 +2222,6 @@ static inline u32 gr_scc_pagepool_valid_true_f(void)
{
return 0x80000000U;
}
static inline u32 gr_scc_init_r(void)
{
return 0x0040802cU;
}
static inline u32 gr_scc_init_ram_trigger_f(void)
{
return 0x1U;
}
static inline u32 gr_scc_hww_esr_r(void)
{
return 0x00408030U;

10
drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_gr_gv100.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2017-2019, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -2418,14 +2418,6 @@ static inline u32 gr_scc_pagepool_valid_true_f(void)
{
return 0x80000000U;
}
static inline u32 gr_scc_init_r(void)
{
return 0x0040802cU;
}
static inline u32 gr_scc_init_ram_trigger_f(void)
{
return 0x1U;
}
static inline u32 gr_scc_hww_esr_r(void)
{
return 0x00408030U;

8
drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h
View File

@@ -3082,14 +3082,6 @@ static inline u32 gr_scc_pagepool_valid_true_f(void)
{
return 0x80000000U;
}
static inline u32 gr_scc_init_r(void)
{
return 0x0040802cU;
}
static inline u32 gr_scc_init_ram_trigger_f(void)
{
return 0x1U;
}
static inline u32 gr_scc_hww_esr_r(void)
{
return 0x00408030U;

8
drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_gr_tu104.h
View File

@@ -2398,14 +2398,6 @@ static inline u32 gr_scc_rm_gfxp_reserve_rtv_cb_size_div_256b_f(u32 v)
{
return (v & 0x1ffU) << 0U;
}
static inline u32 gr_scc_init_r(void)
{
return 0x0040802cU;
}
static inline u32 gr_scc_init_ram_trigger_f(void)
{
return 0x1U;
}
static inline u32 gr_scc_hww_esr_r(void)
{
return 0x00408030U;