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gpu: nvgpu: disable access to PE unit when MIG is enabled

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PE unit belongs to GR pipeline but not compute.
Hence disabled access to the PE register in the GR Boot flow
to prevent following PRIV error when SMC mode is enabled.

PRI timeout: ADR 0x00503018 READ  DATA 0x00000000
FECS_ERRCODE 0xbadf1100
[Error Type]: decode error

Jira NVGPU-6699

Change-Id: Ia6f58258611a010252c7ead46b1b48cbf1b64001
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2514894
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Lakshmanan M <lm@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Debarshi Dutta
2021-04-14 17:01:42 +05:30
committed by mobile promotions
parent 95bfa039f5
commit 0a25376965
1 changed files with 3 additions and 1 deletions
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4
drivers/gpu/nvgpu/common/gr/gr.c
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@@ -232,7 +232,9 @@ static int gr_init_setup_hw(struct gk20a *g, struct nvgpu_gr *gr)
g->ops.gr.init.gpc_mmu(g);
g->ops.gr.init.pes_vsc_stream(g);
if (!nvgpu_is_enabled(g, NVGPU_SUPPORT_MIG)) {
g->ops.gr.init.pes_vsc_stream(g);
}
if (g->ops.priv_ring.set_ppriv_timeout_settings != NULL) {
g->ops.priv_ring.set_ppriv_timeout_settings(g);