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gpu: nvgpu: gp106: fix MISRA 9.3 in mclk

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MISRA Rule 9.3 forbids partially initialized arrays.
Add zero len scripts for transitions from one speed to the same.

Jira NVGPU-890

Change-Id: I237e3f29bcd7fe81558e97e141853def8bbcde61
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1930926
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Thomas Fleury
2018-10-18 17:06:47 -07:00
committed by mobile promotions
parent cafe637112
commit 0a77871bab
1 changed files with 9 additions and 1 deletions
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10
drivers/gpu/nvgpu/gp106/mclk_gp106.c
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@@ -2945,7 +2945,6 @@ struct memory_config {
#undef S
#define S(script) { seq_script_##script, (u32)sizeof(seq_script_##script) }
static struct memory_config mem_config[GP106_NUM_MEM_CONFIG] = {
[GP106_MEM_CONFIG_GDDR5_PG418] = {
.pattern_ptr = memory_pattern_gp106,
@@ -2953,16 +2952,19 @@ static struct memory_config mem_config[GP106_NUM_MEM_CONFIG] = {
sizeof(struct memory_link_training_pattern),
.scripts = {
[GP106_MCLK_LOW_SPEED] = {
[GP106_MCLK_LOW_SPEED] = { NULL, 0},
[GP106_MCLK_MID_SPEED] = S(step33_pg418),
[GP106_MCLK_HIGH_SPEED] = S(step28_pg418),
},
[GP106_MCLK_MID_SPEED] = {
[GP106_MCLK_LOW_SPEED] = S(step33_ls_pg418),
[GP106_MCLK_MID_SPEED] = { NULL, 0 },
[GP106_MCLK_HIGH_SPEED] = S(step28_pg418),
},
[GP106_MCLK_HIGH_SPEED] = {
[GP106_MCLK_LOW_SPEED] = S(step32_ls_pg418),
[GP106_MCLK_MID_SPEED] = S(step32_pg418),
[GP106_MCLK_HIGH_SPEED] = { NULL, 0 },
}
}
},
@@ -2972,16 +2974,19 @@ static struct memory_config mem_config[GP106_NUM_MEM_CONFIG] = {
sizeof(struct memory_link_training_pattern),
.scripts = {
[GP106_MCLK_LOW_SPEED] = {
[GP106_MCLK_LOW_SPEED] = { NULL, 0 },
[GP106_MCLK_MID_SPEED] = S(step33_pg419),
[GP106_MCLK_HIGH_SPEED] = S(step28_pg419),
},
[GP106_MCLK_MID_SPEED] = {
[GP106_MCLK_LOW_SPEED] = S(step33_ls_pg419),
[GP106_MCLK_MID_SPEED] = { NULL, 0 },
[GP106_MCLK_HIGH_SPEED] = S(step29_pg419),
},
[GP106_MCLK_HIGH_SPEED] = {
[GP106_MCLK_LOW_SPEED] = S(step32_ls_pg419),
[GP106_MCLK_MID_SPEED] = S(step32_pg419),
[GP106_MCLK_HIGH_SPEED] = { NULL, 0 },
}
}
},
@@ -2991,16 +2996,19 @@ static struct memory_config mem_config[GP106_NUM_MEM_CONFIG] = {
sizeof(struct memory_link_training_pattern),
.scripts = {
[GP106_MCLK_LOW_SPEED] = {
[GP106_MCLK_LOW_SPEED] = { NULL, 0 },
[GP106_MCLK_MID_SPEED] = S(step33_pg419_12),
[GP106_MCLK_HIGH_SPEED] = S(step28_pg419_12),
},
[GP106_MCLK_MID_SPEED] = {
[GP106_MCLK_LOW_SPEED] = S(step33_ls_pg419_12),
[GP106_MCLK_MID_SPEED] = { NULL, 0 },
[GP106_MCLK_HIGH_SPEED] = S(step29_pg419_12),
},
[GP106_MCLK_HIGH_SPEED] = {
[GP106_MCLK_LOW_SPEED] = S(step32_ls_pg419_12),
[GP106_MCLK_MID_SPEED] = S(step32_pg419_12),
[GP106_MCLK_HIGH_SPEED] = { NULL, 0 },
}
}
}