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gpu: nvgpu: move gv11b fecs_trace HAL to gr/fecs trace unit

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Rename gv11b/fecs_trace_gv11b.* files to
common/gr/fecs_trace/fecs_trace_gv11b.*

Also move HAL API gk20a_fecs_trace_get_buffer_full_mailbox_val()
to gr/fecs_trace unit and rename it as
gm20b_fecs_trace_get_buffer_full_mailbox_val()

Protect gm20b/gv11b HAL code under CONFIG_GK20A_CTXSW_TRACE

Remove tu104/fecs_trace_tu104.* since tu104 will re-use gv11b HAL

Fix g->ops.fecs_trace.get_buffer_full_mailbox_val() for vgpu/gv11b and
use gv11b HAL

Jira NVGPU-1880

Change-Id: If78480e36be4e5f0fd659019518f233d8805486d
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2029259
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Deepak Nibade
2019-02-27 16:09:53 +05:30
committed by mobile promotions
parent 11757aabbd
commit 0aa1ef7c0c
16 changed files with 26 additions and 81 deletions
Download Patch File Download Diff File Expand all files Collapse all files

5
drivers/gpu/nvgpu/Makefile
View File

@@ -90,6 +90,7 @@ nvgpu-y += \
common/gr/config/gr_config_gm20b.o \
common/gr/fecs_trace/fecs_trace.o \
common/gr/fecs_trace/fecs_trace_gm20b.o \
common/gr/fecs_trace/fecs_trace_gv11b.o \
common/gr/zbc/gr_zbc.o \
common/gr/zbc/gr_zbc_gm20b.o \
common/gr/zbc/gr_zbc_gp10b.o \
@@ -388,10 +389,6 @@ nvgpu-y += \
gm20b/fifo_gm20b.o \
gm20b/mm_gm20b.o
nvgpu-$(CONFIG_GK20A_CTXSW_TRACE) += \
gv11b/fecs_trace_gv11b.o \
tu104/fecs_trace_tu104.o \
nvgpu-$(CONFIG_GK20A_VIDMEM) += \
common/mm/vidmem.o

3
drivers/gpu/nvgpu/Makefile.sources
View File

@@ -130,6 +130,7 @@ srcs += common/sim.c \
common/gr/config/gr_config_gm20b.c \
common/gr/fecs_trace/fecs_trace.c \
common/gr/fecs_trace/fecs_trace_gm20b.c \
common/gr/fecs_trace/fecs_trace_gv11b.c \
common/gr/zbc/gr_zbc.c \
common/gr/zbc/gr_zbc_gm20b.c \
common/gr/zbc/gr_zbc_gp10b.c \
@@ -278,7 +279,6 @@ srcs += common/sim.c \
gv11b/mm_gv11b.c \
gv11b/ce_gv11b.c \
gv11b/subctx_gv11b.c \
gv11b/fecs_trace_gv11b.c \
gv11b/ecc_gv11b.c \
gp106/gr_gp106.c \
gp106/sec2_gp106.c \
@@ -309,7 +309,6 @@ srcs += common/sim.c \
tu104/hal_tu104.c \
tu104/sec2_tu104.c \
tu104/func_tu104.c \
tu104/fecs_trace_tu104.c \
common/vgpu/vgpu.c \
common/vgpu/fifo/fifo_vgpu.c \
common/vgpu/fifo/runlist_vgpu.c \

9
drivers/gpu/nvgpu/common/gr/fecs_trace/fecs_trace_gm20b.c
View File

@@ -34,6 +34,8 @@
#include <nvgpu/hw/gm20b/hw_gr_gm20b.h>
#ifdef CONFIG_GK20A_CTXSW_TRACE
int gm20b_fecs_trace_get_read_index(struct gk20a *g)
{
return gr_gk20a_elpg_protected_call(g,
@@ -52,3 +54,10 @@ int gm20b_fecs_trace_set_read_index(struct gk20a *g, int index)
return gr_gk20a_elpg_protected_call(g,
(nvgpu_writel(g, gr_fecs_mailbox1_r(), index), 0));
}
u32 gm20b_fecs_trace_get_buffer_full_mailbox_val(void)
{
return 0x26;
}
#endif /* CONFIG_GK20A_CTXSW_TRACE */

3
drivers/gpu/nvgpu/common/gr/fecs_trace/fecs_trace_gm20b.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -30,5 +30,6 @@ struct gk20a;
int gm20b_fecs_trace_get_read_index(struct gk20a *g);
int gm20b_fecs_trace_get_write_index(struct gk20a *g);
int gm20b_fecs_trace_set_read_index(struct gk20a *g, int index);
u32 gm20b_fecs_trace_get_buffer_full_mailbox_val(void);
#endif /* NVGPU_GR_FECS_TRACE_GM20B_H */

4
drivers/gpu/nvgpu/gv11b/fecs_trace_gv11b.c → drivers/gpu/nvgpu/common/gr/fecs_trace/fecs_trace_gv11b.c
View File

@@ -22,7 +22,11 @@
#include "fecs_trace_gv11b.h"
#ifdef CONFIG_GK20A_CTXSW_TRACE
u32 gv11b_fecs_trace_get_buffer_full_mailbox_val(void)
{
return 0x32;
}
#endif /* CONFIG_GK20A_CTXSW_TRACE */

0
drivers/gpu/nvgpu/gv11b/fecs_trace_gv11b.h → drivers/gpu/nvgpu/common/gr/fecs_trace/fecs_trace_gv11b.h
View File

5
drivers/gpu/nvgpu/common/vgpu/gp10b/vgpu_hal_gp10b.c
View File

@@ -30,6 +30,7 @@
#include "common/gr/ctxsw_prog/ctxsw_prog_gm20b.h"
#include "common/gr/ctxsw_prog/ctxsw_prog_gp10b.h"
#include "common/gr/config/gr_config_gm20b.h"
#include "common/gr/fecs_trace/fecs_trace_gm20b.h"
#include "common/therm/therm_gm20b.h"
#include "common/therm/therm_gp10b.h"
#include "common/ltc/ltc_gm20b.h"
@@ -69,8 +70,6 @@
#include "gm20b/fifo_gm20b.h"
#include "gm20b/mm_gm20b.h"
#include "gk20a/fecs_trace_gk20a.h"
#include <nvgpu/debugger.h>
#include <nvgpu/enabled.h>
#include <nvgpu/vgpu/vgpu.h>
@@ -481,7 +480,7 @@ static const struct gpu_ops vgpu_gp10b_ops = {
.max_entries = vgpu_fecs_trace_max_entries,
.set_filter = vgpu_fecs_trace_set_filter,
.get_buffer_full_mailbox_val =
gk20a_fecs_trace_get_buffer_full_mailbox_val,
gm20b_fecs_trace_get_buffer_full_mailbox_val,
},
#endif /* CONFIG_GK20A_CTXSW_TRACE */
.mm = {

5
drivers/gpu/nvgpu/common/vgpu/gv11b/vgpu_hal_gv11b.c
View File

@@ -31,6 +31,7 @@
#include "common/gr/ctxsw_prog/ctxsw_prog_gm20b.h"
#include "common/gr/ctxsw_prog/ctxsw_prog_gp10b.h"
#include "common/gr/ctxsw_prog/ctxsw_prog_gv11b.h"
#include "common/gr/fecs_trace/fecs_trace_gv11b.h"
#include "common/therm/therm_gm20b.h"
#include "common/therm/therm_gp10b.h"
#include "common/therm/therm_gv11b.h"
@@ -84,8 +85,6 @@
#include <gv100/gr_gv100.h>
#include "gk20a/fecs_trace_gk20a.h"
#include <nvgpu/debugger.h>
#include <nvgpu/enabled.h>
#include <nvgpu/channel.h>
@@ -554,7 +553,7 @@ static const struct gpu_ops vgpu_gv11b_ops = {
.max_entries = vgpu_fecs_trace_max_entries,
.set_filter = vgpu_fecs_trace_set_filter,
.get_buffer_full_mailbox_val =
gk20a_fecs_trace_get_buffer_full_mailbox_val,
gv11b_fecs_trace_get_buffer_full_mailbox_val,
},
#endif /* CONFIG_GK20A_CTXSW_TRACE */
.mm = {

4
drivers/gpu/nvgpu/gk20a/fecs_trace_gk20a.c
View File

@@ -143,8 +143,4 @@ int gk20a_fecs_trace_unbind_channel(struct gk20a *g, struct channel_gk20a *ch)
return 0;
}
u32 gk20a_fecs_trace_get_buffer_full_mailbox_val(void)
{
return 0x26;
}
#endif /* CONFIG_GK20A_CTXSW_TRACE */

1
drivers/gpu/nvgpu/gk20a/fecs_trace_gk20a.h
View File

@@ -32,6 +32,5 @@ int gk20a_fecs_trace_bind_channel(struct gk20a *g,
struct channel_gk20a *ch, u32 vmid,
struct nvgpu_gr_ctx *gr_ctx);
int gk20a_fecs_trace_unbind_channel(struct gk20a *g, struct channel_gk20a *ch);
u32 gk20a_fecs_trace_get_buffer_full_mailbox_val(void);
#endif /* NVGPU_GK20A_FECS_TRACE_GK20A_H */

2
drivers/gpu/nvgpu/gp10b/hal_gp10b.c
View File

@@ -679,7 +679,7 @@ static const struct gpu_ops gp10b_ops = {
.unbind_channel = gk20a_fecs_trace_unbind_channel,
.max_entries = nvgpu_gr_fecs_trace_max_entries,
.get_buffer_full_mailbox_val =
gk20a_fecs_trace_get_buffer_full_mailbox_val,
gm20b_fecs_trace_get_buffer_full_mailbox_val,
.get_read_index = gm20b_fecs_trace_get_read_index,
.get_write_index = gm20b_fecs_trace_get_write_index,
.set_read_index = gm20b_fecs_trace_set_read_index,

2
drivers/gpu/nvgpu/gv100/hal_gv100.c
View File

@@ -846,7 +846,7 @@ static const struct gpu_ops gv100_ops = {
.unbind_channel = gk20a_fecs_trace_unbind_channel,
.max_entries = nvgpu_gr_fecs_trace_max_entries,
.get_buffer_full_mailbox_val =
gk20a_fecs_trace_get_buffer_full_mailbox_val,
gm20b_fecs_trace_get_buffer_full_mailbox_val,
.get_read_index = gm20b_fecs_trace_get_read_index,
.get_write_index = gm20b_fecs_trace_get_write_index,
.set_read_index = gm20b_fecs_trace_set_read_index,

2
drivers/gpu/nvgpu/gv11b/hal_gv11b.c
View File

@@ -44,6 +44,7 @@
#include "common/gr/zbc/gr_zbc_gp10b.h"
#include "common/gr/zbc/gr_zbc_gv11b.h"
#include "common/gr/fecs_trace/fecs_trace_gm20b.h"
#include "common/gr/fecs_trace/fecs_trace_gv11b.h"
#include "common/therm/therm_gm20b.h"
#include "common/therm/therm_gp10b.h"
#include "common/therm/therm_gv11b.h"
@@ -102,7 +103,6 @@
#include "fifo_gv11b.h"
#include "subctx_gv11b.h"
#include "ecc_gv11b.h"
#include "fecs_trace_gv11b.h"
#include <nvgpu/ptimer.h>
#include <nvgpu/debug.h>

28
drivers/gpu/nvgpu/tu104/fecs_trace_tu104.c
View File

@@ -1,28 +0,0 @@
/*
* Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#include "fecs_trace_tu104.h"
u32 tu104_fecs_trace_get_buffer_full_mailbox_val(void)
{
return 0x32;
}

30
drivers/gpu/nvgpu/tu104/fecs_trace_tu104.h
View File

@@ -1,30 +0,0 @@
/*
* Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef NVGPU_FECS_TRACE_TU104_H
#define NVGPU_FECS_TRACE_TU104_H
#include <nvgpu/types.h>
u32 tu104_fecs_trace_get_buffer_full_mailbox_val(void);
#endif /* NVGPU_FECS_TRACE_TU104_H */

4
drivers/gpu/nvgpu/tu104/hal_tu104.c
View File

@@ -46,6 +46,7 @@
#include "common/gr/zbc/gr_zbc_gp10b.h"
#include "common/gr/zbc/gr_zbc_gv11b.h"
#include "common/gr/fecs_trace/fecs_trace_gm20b.h"
#include "common/gr/fecs_trace/fecs_trace_gv11b.h"
#include "common/therm/therm_gm20b.h"
#include "common/therm/therm_gp10b.h"
#include "common/therm/therm_gp106.h"
@@ -137,7 +138,6 @@
#include "tu104/sec2_tu104.h"
#include "tu104/ecc_tu104.h"
#include "tu104/hal_tu104.h"
#include "tu104/fecs_trace_tu104.h"
#include <nvgpu/ptimer.h>
#include <nvgpu/debug.h>
@@ -875,7 +875,7 @@ static const struct gpu_ops tu104_ops = {
.unbind_channel = gk20a_fecs_trace_unbind_channel,
.max_entries = nvgpu_gr_fecs_trace_max_entries,
.get_buffer_full_mailbox_val =
tu104_fecs_trace_get_buffer_full_mailbox_val,
gv11b_fecs_trace_get_buffer_full_mailbox_val,
.get_read_index = gm20b_fecs_trace_get_read_index,
.get_write_index = gm20b_fecs_trace_get_write_index,
.set_read_index = gm20b_fecs_trace_set_read_index,