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gpu: nvgpu: ACR refactor to create ACR unit

Browse Source 
Move ACR code to separate folder under common/acr to
make ACR separate unit. with this, separating ACR blob
construct, bootstrap & ACR chip specific configuration
code to different files.

ACR blob construction code split into two version, as
gm20b & gp10b still uses older ACR interfaces & not yet
moved to Tegra ACR, blob_construct_v0 file can be deleted
once gm20b/gp10b uses Tegra ACR ucode & point to
blob_construct_v1 with simple change.

As ACR ucode can execute on different engine falcon &
should not be dependent on specific engine falcon, used
generic falcon functions/interface to support ACR & doesn't
access any engine h/w registers directly, and files with
chip name has configuration needed for ACR HS ucode & LS
falcons.

JIRA NVGPU-1148

Change-Id: Ieedbe82f3e1a4303f055fbc795d9ce0f1866d259
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2017046
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Mahantesh Kumbar
2019-02-12 12:40:22 +05:30
committed by mobile promotions
parent 0d05c6e159
commit 0aa55f6741
26 changed files with 1592 additions and 1617 deletions
Download Patch File Download Diff File Expand all files Collapse all files

13
drivers/gpu/nvgpu/Makefile
View File

@@ -114,11 +114,14 @@ nvgpu-y += common/bus/bus_gk20a.o \
common/pmu/pmu_gv11b.o \
common/pmu/pmu_gv100.o \
common/pmu/pmu_tu104.o \
common/pmu/acr_gm20b.o \
common/pmu/acr_gp10b.o \
common/pmu/acr_gp106.o \
common/pmu/acr_gv11b.o \
common/pmu/acr_tu104.o \
common/acr/acr.o \
common/acr/acr_blob_construct_v0.o \
common/acr/acr_blob_construct_v1.o \
common/acr/acr_gm20b.o \
common/acr/acr_gp10b.o \
common/acr/acr_gv100.o \
common/acr/acr_gv11b.o \
common/acr/acr_tu104.o \
common/pmu/perf/vfe_var.o \
common/pmu/perf/vfe_equ.o \
common/pmu/perf/pmu_perf.o \

13
drivers/gpu/nvgpu/Makefile.sources
View File

@@ -153,11 +153,14 @@ srcs += common/sim.c \
common/pmu/pmu_gv11b.c \
common/pmu/pmu_gv100.c \
common/pmu/pmu_tu104.c \
common/pmu/acr_gm20b.c \
common/pmu/acr_gp10b.c \
common/pmu/acr_gp106.c \
common/pmu/acr_gv11b.c \
common/pmu/acr_tu104.c \
common/acr/acr.c \
common/acr/acr_blob_construct_v0.c \
common/acr/acr_blob_construct_v1.c \
common/acr/acr_gm20b.c \
common/acr/acr_gp10b.c \
common/acr/acr_gv100.c \
common/acr/acr_gv11b.c \
common/acr/acr_tu104.c \
common/sec2/sec2.c \
common/sec2/sec2_ipc.c \
common/ptimer/ptimer.c \

337
drivers/gpu/nvgpu/common/acr/acr.c Normal file
View File

@@ -0,0 +1,337 @@
/*
* Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#include <nvgpu/types.h>
#include <nvgpu/dma.h>
#include <nvgpu/timers.h>
#include <nvgpu/nvgpu_mem.h>
#include <nvgpu/acr/nvgpu_acr.h>
#include <nvgpu/firmware.h>
#include <nvgpu/pmu.h>
#include <nvgpu/falcon.h>
#include <nvgpu/gk20a.h>
#include <nvgpu/bug.h>
/* Both size and address of WPR need to be 128K-aligned */
#define DGPU_WPR_SIZE 0x200000U
static int acr_wait_for_completion(struct gk20a *g,
struct nvgpu_falcon *flcn, unsigned int timeout)
{
u32 flcn_id = nvgpu_falcon_get_id(flcn);
u32 sctl, cpuctl;
int completion = 0;
u32 data = 0;
nvgpu_log_fn(g, " ");
completion = nvgpu_falcon_wait_for_halt(flcn, timeout);
if (completion != 0) {
nvgpu_err(g, "flcn-%d: ACR boot timed out", flcn_id);
goto exit;
}
nvgpu_acr_dbg(g, "flcn-%d: ACR capabilities %x", flcn_id,
nvgpu_falcon_mailbox_read(flcn, FALCON_MAILBOX_1));
data = nvgpu_falcon_mailbox_read(flcn, FALCON_MAILBOX_0);
if (data != 0U) {
nvgpu_err(g, "flcn-%d: ACR boot failed, err %x", flcn_id,
data);
completion = -EAGAIN;
goto exit;
}
nvgpu_falcon_get_ctls(flcn, &sctl, &cpuctl);
nvgpu_acr_dbg(g, "flcn-%d: sctl reg %x cpuctl reg %x",
flcn_id, sctl, cpuctl);
exit:
return completion;
}
static int acr_hs_bl_exec(struct gk20a *g, struct nvgpu_acr *acr,
struct hs_acr *acr_desc, bool b_wait_for_halt)
{
struct nvgpu_firmware *hs_bl_fw = acr_desc->acr_hs_bl.hs_bl_fw;
struct hsflcn_bl_desc *hs_bl_desc;
struct nvgpu_falcon_bl_info bl_info;
struct hs_flcn_bl *hs_bl = &acr_desc->acr_hs_bl;
struct mm_gk20a *mm = &g->mm;
struct vm_gk20a *vm = mm->pmu.vm;
u32 flcn_id = nvgpu_falcon_get_id(acr_desc->acr_flcn);
u32 *hs_bl_code = NULL;
int err = 0;
u32 bl_sz;
nvgpu_acr_dbg(g, "Executing ACR HS Bootloader %s on Falcon-ID - %d",
hs_bl->bl_fw_name, flcn_id);
if (hs_bl_fw == NULL) {
hs_bl_fw = nvgpu_request_firmware(g, hs_bl->bl_fw_name, 0);
if (hs_bl_fw == NULL) {
nvgpu_err(g, "ACR HS BL ucode load fail");
return -ENOENT;
}
hs_bl->hs_bl_fw = hs_bl_fw;
hs_bl->hs_bl_bin_hdr = (struct bin_hdr *)hs_bl_fw->data;
hs_bl->hs_bl_desc = (struct hsflcn_bl_desc *)(hs_bl_fw->data +
hs_bl->hs_bl_bin_hdr->header_offset);
hs_bl_desc = hs_bl->hs_bl_desc;
hs_bl_code = (u32 *)(hs_bl_fw->data +
hs_bl->hs_bl_bin_hdr->data_offset);
bl_sz = ALIGN(hs_bl_desc->bl_img_hdr.bl_code_size, 256U);
hs_bl->hs_bl_ucode.size = bl_sz;
err = nvgpu_dma_alloc_sys(g, bl_sz, &hs_bl->hs_bl_ucode);
if (err != 0) {
nvgpu_err(g, "ACR HS BL failed to allocate memory");
goto err_done;
}
hs_bl->hs_bl_ucode.gpu_va = nvgpu_gmmu_map(vm,
&hs_bl->hs_bl_ucode,
bl_sz,
0U, /* flags */
gk20a_mem_flag_read_only, false,
hs_bl->hs_bl_ucode.aperture);
if (hs_bl->hs_bl_ucode.gpu_va == 0U) {
nvgpu_err(g, "ACR HS BL failed to map ucode memory!!");
goto err_free_ucode;
}
nvgpu_mem_wr_n(g, &hs_bl->hs_bl_ucode, 0U, hs_bl_code, bl_sz);
nvgpu_acr_dbg(g, "Copied BL ucode to bl_cpuva");
}
/* Fill HS BL info */
bl_info.bl_src = hs_bl->hs_bl_ucode.cpu_va;
bl_info.bl_desc = acr_desc->ptr_bl_dmem_desc;
nvgpu_assert(acr_desc->bl_dmem_desc_size <= U32_MAX);
bl_info.bl_desc_size = (u32)acr_desc->bl_dmem_desc_size;
nvgpu_assert(hs_bl->hs_bl_ucode.size <= U32_MAX);
bl_info.bl_size = (u32)hs_bl->hs_bl_ucode.size;
bl_info.bl_start_tag = hs_bl->hs_bl_desc->bl_start_tag;
/*
* 1. Does falcon reset
* 2. setup falcon apertures
* 3. bootstrap falcon
*/
acr_desc->acr_flcn_setup_hw_and_bl_bootstrap(g, acr_desc, &bl_info);
if (b_wait_for_halt) {
/* wait for ACR halt*/
err = acr_wait_for_completion(g, acr_desc->acr_flcn,
ACR_COMPLETION_TIMEOUT_MS);
if (err != 0) {
goto err_unmap_bl;
}
}
return 0;
err_unmap_bl:
nvgpu_gmmu_unmap(vm, &hs_bl->hs_bl_ucode, hs_bl->hs_bl_ucode.gpu_va);
err_free_ucode:
nvgpu_dma_free(g, &hs_bl->hs_bl_ucode);
err_done:
nvgpu_release_firmware(g, hs_bl_fw);
acr_desc->acr_hs_bl.hs_bl_fw = NULL;
return err;
}
/*
* Patch signatures into ucode image
*/
static int acr_ucode_patch_sig(struct gk20a *g,
unsigned int *p_img, unsigned int *p_prod_sig,
unsigned int *p_dbg_sig, unsigned int *p_patch_loc,
unsigned int *p_patch_ind)
{
unsigned int i, *p_sig;
nvgpu_acr_dbg(g, " ");
if (!g->ops.pmu.is_debug_mode_enabled(g)) {
p_sig = p_prod_sig;
nvgpu_acr_dbg(g, "PRODUCTION MODE\n");
} else {
p_sig = p_dbg_sig;
nvgpu_acr_dbg(g, "DEBUG MODE\n");
}
/* Patching logic:*/
for (i = 0U; i < sizeof(*p_patch_loc)>>2U; i++) {
p_img[(p_patch_loc[i]>>2U)] = p_sig[(p_patch_ind[i]<<2U)];
p_img[(p_patch_loc[i]>>2U)+1U] = p_sig[(p_patch_ind[i]<<2U)+1U];
p_img[(p_patch_loc[i]>>2U)+2U] = p_sig[(p_patch_ind[i]<<2U)+2U];
p_img[(p_patch_loc[i]>>2U)+3U] = p_sig[(p_patch_ind[i]<<2U)+3U];
}
return 0;
}
/*
* Loads ACR bin to SYSMEM/FB and bootstraps ACR with bootloader code
* start and end are addresses of ucode blob in non-WPR region
*/
int nvgpu_acr_bootstrap_hs_ucode(struct gk20a *g, struct nvgpu_acr *acr,
struct hs_acr *acr_desc)
{
struct mm_gk20a *mm = &g->mm;
struct vm_gk20a *vm = mm->pmu.vm;
struct nvgpu_firmware *acr_fw = acr_desc->acr_fw;
struct bin_hdr *acr_fw_bin_hdr = NULL;
struct acr_fw_header *acr_fw_hdr = NULL;
struct nvgpu_mem *acr_ucode_mem = &acr_desc->acr_ucode;
u32 img_size_in_bytes = 0;
u32 *acr_ucode_data;
u32 *acr_ucode_header;
int status = 0;
nvgpu_acr_dbg(g, "ACR TYPE %x ", acr_desc->acr_type);
if (acr_fw != NULL) {
acr->patch_wpr_info_to_ucode(g, acr, acr_desc, true);
} else {
acr_fw = nvgpu_request_firmware(g, acr_desc->acr_fw_name,
NVGPU_REQUEST_FIRMWARE_NO_SOC);
if (acr_fw == NULL) {
nvgpu_err(g, "%s ucode get fail for %s",
acr_desc->acr_fw_name, g->name);
return -ENOENT;
}
acr_desc->acr_fw = acr_fw;
acr_fw_bin_hdr = (struct bin_hdr *)acr_fw->data;
acr_fw_hdr = (struct acr_fw_header *)
(acr_fw->data + acr_fw_bin_hdr->header_offset);
acr_ucode_header = (u32 *)(acr_fw->data +
acr_fw_hdr->hdr_offset);
acr_ucode_data = (u32 *)(acr_fw->data +
acr_fw_bin_hdr->data_offset);
img_size_in_bytes = ALIGN((acr_fw_bin_hdr->data_size), 256U);
/* Lets patch the signatures first.. */
if (acr_ucode_patch_sig(g, acr_ucode_data,
(u32 *)(acr_fw->data + acr_fw_hdr->sig_prod_offset),
(u32 *)(acr_fw->data + acr_fw_hdr->sig_dbg_offset),
(u32 *)(acr_fw->data + acr_fw_hdr->patch_loc),
(u32 *)(acr_fw->data + acr_fw_hdr->patch_sig)) < 0) {
nvgpu_err(g, "patch signatures fail");
status = -1;
goto err_release_acr_fw;
}
status = nvgpu_dma_alloc_map_sys(vm, img_size_in_bytes,
acr_ucode_mem);
if (status != 0) {
status = -ENOMEM;
goto err_release_acr_fw;
}
acr->patch_wpr_info_to_ucode(g, acr, acr_desc, false);
nvgpu_mem_wr_n(g, acr_ucode_mem, 0U, acr_ucode_data,
img_size_in_bytes);
/*
* In order to execute this binary, we will be using
* a bootloader which will load this image into
* FALCON IMEM/DMEM.
* Fill up the bootloader descriptor to use..
* TODO: Use standard descriptor which the generic bootloader is
* checked in.
*/
acr->acr_fill_bl_dmem_desc(g, acr, acr_desc, acr_ucode_header);
}
status = acr_hs_bl_exec(g, acr, acr_desc, true);
if (status != 0) {
goto err_free_ucode_map;
}
return 0;
err_free_ucode_map:
nvgpu_dma_unmap_free(vm, acr_ucode_mem);
err_release_acr_fw:
nvgpu_release_firmware(g, acr_fw);
acr_desc->acr_fw = NULL;
return status;
}
int nvgpu_acr_alloc_blob_space_sys(struct gk20a *g, size_t size,
struct nvgpu_mem *mem)
{
return nvgpu_dma_alloc_flags_sys(g, NVGPU_DMA_PHYSICALLY_ADDRESSED,
size, mem);
}
int nvgpu_acr_alloc_blob_space_vid(struct gk20a *g, size_t size,
struct nvgpu_mem *mem)
{
struct wpr_carveout_info wpr_inf;
int err;
if (mem->size != 0ULL) {
return 0;
}
g->acr.get_wpr_info(g, &wpr_inf);
/*
* Even though this mem_desc wouldn't be used, the wpr region needs to
* be reserved in the allocator.
*/
err = nvgpu_dma_alloc_vid_at(g, wpr_inf.size,
&g->acr.wpr_dummy, wpr_inf.wpr_base);
if (err != 0) {
return err;
}
return nvgpu_dma_alloc_vid_at(g, wpr_inf.size, mem,
wpr_inf.nonwpr_base);
}
void nvgpu_acr_wpr_info_sys(struct gk20a *g, struct wpr_carveout_info *inf)
{
g->ops.fb.read_wpr_info(g, inf);
}
void nvgpu_acr_wpr_info_vid(struct gk20a *g, struct wpr_carveout_info *inf)
{
inf->wpr_base = g->mm.vidmem.bootstrap_base;
inf->nonwpr_base = inf->wpr_base + DGPU_WPR_SIZE;
inf->size = DGPU_WPR_SIZE;
}

1114
drivers/gpu/nvgpu/common/pmu/acr_gm20b.c → drivers/gpu/nvgpu/common/acr/acr_blob_construct_v0.c
View File

File diff suppressed because it is too large Load Diff

1100
drivers/gpu/nvgpu/common/pmu/acr_gp106.c → drivers/gpu/nvgpu/common/acr/acr_blob_construct_v1.c
View File

File diff suppressed because it is too large Load Diff

219
drivers/gpu/nvgpu/common/acr/acr_gm20b.c Normal file
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@@ -0,0 +1,219 @@
/*
* Copyright (c) 2015-2019, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#include <nvgpu/types.h>
#include <nvgpu/acr/nvgpu_acr.h>
#include <nvgpu/firmware.h>
#include <nvgpu/pmu.h>
#include <nvgpu/falcon.h>
#include <nvgpu/gk20a.h>
#include <nvgpu/bug.h>
#include "common/pmu/pmu_gm20b.h"
#include "acr_gm20b.h"
static int gm20b_acr_patch_wpr_info_to_ucode(struct gk20a *g,
struct nvgpu_acr *acr, struct hs_acr *acr_desc, bool is_recovery)
{
struct nvgpu_firmware *acr_fw = acr_desc->acr_fw;
struct acr_fw_header *acr_fw_hdr = NULL;
struct bin_hdr *acr_fw_bin_hdr = NULL;
struct flcn_acr_desc *acr_dmem_desc;
u32 *acr_ucode_header = NULL;
u32 *acr_ucode_data = NULL;
nvgpu_log_fn(g, " ");
if (is_recovery) {
acr_desc->acr_dmem_desc->nonwpr_ucode_blob_size = 0U;
} else {
acr_fw_bin_hdr = (struct bin_hdr *)acr_fw->data;
acr_fw_hdr = (struct acr_fw_header *)
(acr_fw->data + acr_fw_bin_hdr->header_offset);
acr_ucode_data = (u32 *)(acr_fw->data +
acr_fw_bin_hdr->data_offset);
acr_ucode_header = (u32 *)(acr_fw->data +
acr_fw_hdr->hdr_offset);
/* During recovery need to update blob size as 0x0*/
acr_desc->acr_dmem_desc = (struct flcn_acr_desc *)((u8 *)(
acr_desc->acr_ucode.cpu_va) + acr_ucode_header[2U]);
/* Patch WPR info to ucode */
acr_dmem_desc = (struct flcn_acr_desc *)
&(((u8 *)acr_ucode_data)[acr_ucode_header[2U]]);
acr_dmem_desc->nonwpr_ucode_blob_start =
nvgpu_mem_get_addr(g, &g->acr.ucode_blob);
nvgpu_assert(g->acr.ucode_blob.size <= U32_MAX);
acr_dmem_desc->nonwpr_ucode_blob_size =
(u32)g->acr.ucode_blob.size;
acr_dmem_desc->regions.no_regions = 1U;
acr_dmem_desc->wpr_offset = 0U;
}
return 0;
}
static int gm20b_acr_fill_bl_dmem_desc(struct gk20a *g,
struct nvgpu_acr *acr, struct hs_acr *acr_desc,
u32 *acr_ucode_header)
{
struct flcn_bl_dmem_desc *bl_dmem_desc = &acr_desc->bl_dmem_desc;
nvgpu_log_fn(g, " ");
(void) memset(bl_dmem_desc, 0U, sizeof(struct flcn_bl_dmem_desc));
bl_dmem_desc->signature[0] = 0U;
bl_dmem_desc->signature[1] = 0U;
bl_dmem_desc->signature[2] = 0U;
bl_dmem_desc->signature[3] = 0U;
bl_dmem_desc->ctx_dma = GK20A_PMU_DMAIDX_VIRT;
bl_dmem_desc->code_dma_base =
(unsigned int)(((u64)acr_desc->acr_ucode.gpu_va >> 8U));
bl_dmem_desc->code_dma_base1 = 0x0U;
bl_dmem_desc->non_sec_code_off = acr_ucode_header[0U];
bl_dmem_desc->non_sec_code_size = acr_ucode_header[1U];
bl_dmem_desc->sec_code_off = acr_ucode_header[5U];
bl_dmem_desc->sec_code_size = acr_ucode_header[6U];
bl_dmem_desc->code_entry_point = 0U; /* Start at 0th offset */
bl_dmem_desc->data_dma_base =
bl_dmem_desc->code_dma_base +
((acr_ucode_header[2U]) >> 8U);
bl_dmem_desc->data_dma_base1 = 0x0U;
bl_dmem_desc->data_size = acr_ucode_header[3U];
return 0;
}
/* LSF static config functions */
static u32 gm20b_acr_lsf_pmu(struct gk20a *g,
struct acr_lsf_config *lsf)
{
/* PMU LS falcon info */
lsf->falcon_id = FALCON_ID_PMU;
lsf->falcon_dma_idx = GK20A_PMU_DMAIDX_UCODE;
lsf->is_lazy_bootstrap = false;
lsf->is_priv_load = false;
lsf->get_lsf_ucode_details = nvgpu_acr_lsf_pmu_ucode_details_v0;
lsf->get_cmd_line_args_offset = nvgpu_pmu_get_cmd_line_args_offset;
return BIT32(lsf->falcon_id);
}
static u32 gm20b_acr_lsf_fecs(struct gk20a *g,
struct acr_lsf_config *lsf)
{
/* FECS LS falcon info */
lsf->falcon_id = FALCON_ID_FECS;
lsf->falcon_dma_idx = GK20A_PMU_DMAIDX_UCODE;
lsf->is_lazy_bootstrap = false;
lsf->is_priv_load = false;
lsf->get_lsf_ucode_details = nvgpu_acr_lsf_fecs_ucode_details_v0;
lsf->get_cmd_line_args_offset = NULL;
return BIT32(lsf->falcon_id);
}
static u32 gm20b_acr_lsf_conifg(struct gk20a *g,
struct nvgpu_acr *acr)
{
u32 lsf_enable_mask = 0;
lsf_enable_mask |= gm20b_acr_lsf_pmu(g, &acr->lsf[FALCON_ID_PMU]);
lsf_enable_mask |= gm20b_acr_lsf_fecs(g, &acr->lsf[FALCON_ID_FECS]);
return lsf_enable_mask;
}
static void gm20b_acr_default_sw_init(struct gk20a *g, struct hs_acr *hs_acr)
{
struct hs_flcn_bl *hs_bl = &hs_acr->acr_hs_bl;
nvgpu_log_fn(g, " ");
/* ACR HS bootloader ucode name */
hs_bl->bl_fw_name = HSBIN_ACR_BL_UCODE_IMAGE;
/* ACR HS ucode type & f/w name*/
hs_acr->acr_type = ACR_DEFAULT;
hs_acr->acr_fw_name = HSBIN_ACR_UCODE_IMAGE;
/* bootlader interface used by ACR HS bootloader*/
hs_acr->ptr_bl_dmem_desc = &hs_acr->bl_dmem_desc;
hs_acr->bl_dmem_desc_size = (u32)sizeof(struct flcn_bl_dmem_desc);
/* set on which falcon ACR need to execute*/
hs_acr->acr_flcn = g->pmu.flcn;
hs_acr->acr_flcn_setup_hw_and_bl_bootstrap =
gm20b_pmu_setup_hw_and_bl_bootstrap;
}
void gm20b_remove_acr_support(struct nvgpu_acr *acr)
{
struct gk20a *g = acr->g;
struct mm_gk20a *mm = &g->mm;
struct vm_gk20a *vm = mm->pmu.vm;
if (acr->acr.acr_fw != NULL) {
nvgpu_release_firmware(g, acr->acr.acr_fw);
}
if (acr->acr.acr_hs_bl.hs_bl_fw != NULL) {
nvgpu_release_firmware(g, acr->acr.acr_hs_bl.hs_bl_fw);
}
if (nvgpu_mem_is_valid(&acr->acr.acr_ucode)) {
nvgpu_dma_unmap_free(vm, &acr->acr.acr_ucode);
}
if (nvgpu_mem_is_valid(&acr->acr.acr_hs_bl.hs_bl_ucode)) {
nvgpu_dma_unmap_free(vm, &acr->acr.acr_hs_bl.hs_bl_ucode);
}
}
void nvgpu_gm20b_acr_sw_init(struct gk20a *g, struct nvgpu_acr *acr)
{
nvgpu_log_fn(g, " ");
acr->g = g;
acr->bootstrap_owner = FALCON_ID_PMU;
acr->lsf_enable_mask = gm20b_acr_lsf_conifg(g, acr);
gm20b_acr_default_sw_init(g, &acr->acr);
acr->prepare_ucode_blob = nvgpu_acr_prepare_ucode_blob_v0;
acr->get_wpr_info = nvgpu_acr_wpr_info_sys;
acr->alloc_blob_space = nvgpu_acr_alloc_blob_space_sys;
acr->bootstrap_hs_acr = nvgpu_acr_bootstrap_hs_ucode;
acr->patch_wpr_info_to_ucode =
gm20b_acr_patch_wpr_info_to_ucode;
acr->acr_fill_bl_dmem_desc =
gm20b_acr_fill_bl_dmem_desc;
acr->remove_support = gm20b_remove_acr_support;
}

21
drivers/gpu/nvgpu/common/pmu/acr_gm20b.h → drivers/gpu/nvgpu/common/acr/acr_gm20b.h
View File

@@ -25,27 +25,6 @@
#ifndef NVGPU_GM20B_ACR_GM20B_H
#define NVGPU_GM20B_ACR_GM20B_H
#define GM20B_FECS_UCODE_SIG "fecs_sig.bin"
#define T18x_GPCCS_UCODE_SIG "gpccs_sig.bin"
int prepare_ucode_blob(struct gk20a *g);
int acr_ucode_patch_sig(struct gk20a *g,
unsigned int *p_img,
unsigned int *p_prod_sig,
unsigned int *p_dbg_sig,
unsigned int *p_patch_loc,
unsigned int *p_patch_ind);
int gm20b_alloc_blob_space(struct gk20a *g,
size_t size, struct nvgpu_mem *mem);
void gm20b_wpr_info(struct gk20a *g, struct wpr_carveout_info *inf);
int gm20b_acr_patch_wpr_info_to_ucode(struct gk20a *g,
struct nvgpu_acr *acr, struct hs_acr *acr_desc, bool is_recovery);
int gm20b_acr_fill_bl_dmem_desc(struct gk20a *g,
struct nvgpu_acr *acr, struct hs_acr *acr_desc,
u32 *acr_ucode_header);
int gm20b_bootstrap_hs_acr(struct gk20a *g, struct nvgpu_acr *acr,
struct hs_acr *acr_desc);
void gm20b_remove_acr_support(struct nvgpu_acr *acr);
void nvgpu_gm20b_acr_sw_init(struct gk20a *g, struct nvgpu_acr *acr);

3
drivers/gpu/nvgpu/common/pmu/acr_gp10b.c → drivers/gpu/nvgpu/common/acr/acr_gp10b.c
View File

@@ -28,7 +28,6 @@
#include "acr_gm20b.h"
#include "acr_gp10b.h"
/* LSF static config functions */
static u32 gp10b_acr_lsf_gpccs(struct gk20a *g,
struct acr_lsf_config *lsf)
@@ -38,7 +37,7 @@ static u32 gp10b_acr_lsf_gpccs(struct gk20a *g,
lsf->falcon_dma_idx = GK20A_PMU_DMAIDX_UCODE;
lsf->is_lazy_bootstrap = true;
lsf->is_priv_load = true;
lsf->get_lsf_ucode_details = NULL;
lsf->get_lsf_ucode_details = nvgpu_acr_lsf_gpccs_ucode_details_v0;
lsf->get_cmd_line_args_offset = NULL;
return BIT32(lsf->falcon_id);

0
drivers/gpu/nvgpu/common/pmu/acr_gp10b.h → drivers/gpu/nvgpu/common/acr/acr_gp10b.h
View File

214
drivers/gpu/nvgpu/common/acr/acr_gv100.c Normal file
View File

@@ -0,0 +1,214 @@
/*
* Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#include <nvgpu/acr/nvgpu_acr.h>
#include <nvgpu/firmware.h>
#include <nvgpu/pmu.h>
#include <nvgpu/gk20a.h>
#include <nvgpu/bug.h>
#include "acr_gm20b.h"
#include "acr_gv100.h"
#include "gp106/sec2_gp106.h"
static void flcn64_set_dma(struct falc_u64 *dma_addr, u64 value)
{
dma_addr->lo |= u64_lo32(value);
dma_addr->hi |= u64_hi32(value);
}
static int gv100_acr_patch_wpr_info_to_ucode(struct gk20a *g, struct nvgpu_acr *acr,
struct hs_acr *acr_desc, bool is_recovery)
{
struct nvgpu_firmware *acr_fw = acr_desc->acr_fw;
struct acr_fw_header *acr_fw_hdr = NULL;
struct bin_hdr *acr_fw_bin_hdr = NULL;
struct flcn_acr_desc_v1 *acr_dmem_desc;
struct wpr_carveout_info wpr_inf;
u32 *acr_ucode_header = NULL;
u32 *acr_ucode_data = NULL;
nvgpu_log_fn(g, " ");
acr_fw_bin_hdr = (struct bin_hdr *)acr_fw->data;
acr_fw_hdr = (struct acr_fw_header *)
(acr_fw->data + acr_fw_bin_hdr->header_offset);
acr_ucode_data = (u32 *)(acr_fw->data + acr_fw_bin_hdr->data_offset);
acr_ucode_header = (u32 *)(acr_fw->data + acr_fw_hdr->hdr_offset);
acr->get_wpr_info(g, &wpr_inf);
acr_dmem_desc = (struct flcn_acr_desc_v1 *)
&(((u8 *)acr_ucode_data)[acr_ucode_header[2U]]);
acr_dmem_desc->nonwpr_ucode_blob_start = wpr_inf.nonwpr_base;
nvgpu_assert(wpr_inf.size <= U32_MAX);
acr_dmem_desc->nonwpr_ucode_blob_size = (u32)wpr_inf.size;
acr_dmem_desc->regions.no_regions = 1U;
acr_dmem_desc->wpr_offset = 0U;
acr_dmem_desc->wpr_region_id = 1U;
acr_dmem_desc->regions.region_props[0U].region_id = 1U;
acr_dmem_desc->regions.region_props[0U].start_addr =
(wpr_inf.wpr_base) >> 8U;
acr_dmem_desc->regions.region_props[0U].end_addr =
((wpr_inf.wpr_base) + wpr_inf.size) >> 8U;
acr_dmem_desc->regions.region_props[0U].shadowmMem_startaddress =
wpr_inf.nonwpr_base >> 8U;
return 0;
}
int gv100_acr_fill_bl_dmem_desc(struct gk20a *g,
struct nvgpu_acr *acr, struct hs_acr *acr_desc,
u32 *acr_ucode_header)
{
struct nvgpu_mem *acr_ucode_mem = &acr_desc->acr_ucode;
struct flcn_bl_dmem_desc_v1 *bl_dmem_desc =
&acr_desc->bl_dmem_desc_v1;
nvgpu_log_fn(g, " ");
(void) memset(bl_dmem_desc, 0U, sizeof(struct flcn_bl_dmem_desc_v1));
bl_dmem_desc->signature[0] = 0U;
bl_dmem_desc->signature[1] = 0U;
bl_dmem_desc->signature[2] = 0U;
bl_dmem_desc->signature[3] = 0U;
bl_dmem_desc->ctx_dma = GK20A_PMU_DMAIDX_VIRT;
flcn64_set_dma(&bl_dmem_desc->code_dma_base,
acr_ucode_mem->gpu_va);
bl_dmem_desc->non_sec_code_off = acr_ucode_header[0U];
bl_dmem_desc->non_sec_code_size = acr_ucode_header[1U];
bl_dmem_desc->sec_code_off = acr_ucode_header[5U];
bl_dmem_desc->sec_code_size = acr_ucode_header[6U];
bl_dmem_desc->code_entry_point = 0U;
flcn64_set_dma(&bl_dmem_desc->data_dma_base,
acr_ucode_mem->gpu_va + acr_ucode_header[2U]);
bl_dmem_desc->data_size = acr_ucode_header[3U];
return 0;
}
/* LSF init */
static u32 gv100_acr_lsf_pmu(struct gk20a *g,
struct acr_lsf_config *lsf)
{
/* PMU LS falcon info */
lsf->falcon_id = FALCON_ID_PMU;
lsf->falcon_dma_idx = GK20A_PMU_DMAIDX_UCODE;
lsf->is_lazy_bootstrap = false;
lsf->is_priv_load = false;
lsf->get_lsf_ucode_details = nvgpu_acr_lsf_pmu_ucode_details_v1;
lsf->get_cmd_line_args_offset = nvgpu_pmu_get_cmd_line_args_offset;
return BIT32(lsf->falcon_id);
}
static u32 gv100_acr_lsf_fecs(struct gk20a *g,
struct acr_lsf_config *lsf)
{
/* FECS LS falcon info */
lsf->falcon_id = FALCON_ID_FECS;
lsf->falcon_dma_idx = GK20A_PMU_DMAIDX_UCODE;
lsf->is_lazy_bootstrap = true;
lsf->is_priv_load = true;
lsf->get_lsf_ucode_details = nvgpu_acr_lsf_fecs_ucode_details_v1;
lsf->get_cmd_line_args_offset = NULL;
return BIT32(lsf->falcon_id);
}
static u32 gv100_acr_lsf_gpccs(struct gk20a *g,
struct acr_lsf_config *lsf)
{
/* FECS LS falcon info */
lsf->falcon_id = FALCON_ID_GPCCS;
lsf->falcon_dma_idx = GK20A_PMU_DMAIDX_UCODE;
lsf->is_lazy_bootstrap = true;
lsf->is_priv_load = true;
lsf->get_lsf_ucode_details = nvgpu_acr_lsf_gpccs_ucode_details_v1;
lsf->get_cmd_line_args_offset = NULL;
return BIT32(lsf->falcon_id);
}
static u32 gv100_acr_lsf_conifg(struct gk20a *g,
struct nvgpu_acr *acr)
{
u32 lsf_enable_mask = 0;
lsf_enable_mask |= gv100_acr_lsf_pmu(g, &acr->lsf[FALCON_ID_PMU]);
lsf_enable_mask |= gv100_acr_lsf_fecs(g, &acr->lsf[FALCON_ID_FECS]);
lsf_enable_mask |= gv100_acr_lsf_gpccs(g, &acr->lsf[FALCON_ID_GPCCS]);
return lsf_enable_mask;
}
static void nvgpu_gv100_acr_default_sw_init(struct gk20a *g, struct hs_acr *hs_acr)
{
struct hs_flcn_bl *hs_bl = &hs_acr->acr_hs_bl;
nvgpu_log_fn(g, " ");
hs_bl->bl_fw_name = HSBIN_ACR_BL_UCODE_IMAGE;
hs_acr->acr_type = ACR_DEFAULT;
hs_acr->acr_fw_name = HSBIN_ACR_UCODE_IMAGE;
hs_acr->ptr_bl_dmem_desc = &hs_acr->bl_dmem_desc_v1;
hs_acr->bl_dmem_desc_size = (u32)sizeof(struct flcn_bl_dmem_desc_v1);
hs_acr->acr_flcn = g->sec2.flcn;
hs_acr->acr_flcn_setup_hw_and_bl_bootstrap =
gp106_sec2_setup_hw_and_bl_bootstrap;
}
void nvgpu_gv100_acr_sw_init(struct gk20a *g, struct nvgpu_acr *acr)
{
nvgpu_log_fn(g, " ");
acr->g = g;
acr->bootstrap_owner = FALCON_ID_SEC2;
acr->lsf_enable_mask = gv100_acr_lsf_conifg(g, acr);
nvgpu_gv100_acr_default_sw_init(g, &acr->acr);
acr->prepare_ucode_blob = nvgpu_acr_prepare_ucode_blob_v1;
acr->get_wpr_info = nvgpu_acr_wpr_info_vid;
acr->alloc_blob_space = nvgpu_acr_alloc_blob_space_vid;
acr->bootstrap_hs_acr = nvgpu_acr_bootstrap_hs_ucode;
acr->patch_wpr_info_to_ucode =
gv100_acr_patch_wpr_info_to_ucode;
acr->acr_fill_bl_dmem_desc =
gv100_acr_fill_bl_dmem_desc;
acr->remove_support = gm20b_remove_acr_support;
}

5
drivers/gpu/nvgpu/common/pmu/acr_gv100.h → drivers/gpu/nvgpu/common/acr/acr_gv100.h
View File

@@ -26,4 +26,9 @@
#define GV100_FECS_UCODE_SIG "gv100/fecs_sig.bin"
#define GV100_GPCCS_UCODE_SIG "gv100/gpccs_sig.bin"
int gv100_acr_fill_bl_dmem_desc(struct gk20a *g, struct nvgpu_acr *acr,
struct hs_acr *acr_desc, u32 *acr_ucode_header);
void nvgpu_gv100_acr_sw_init(struct gk20a *g, struct nvgpu_acr *acr);
#endif /* NVGPU_ACR_GV100_H */

23
drivers/gpu/nvgpu/common/pmu/acr_gv11b.c → drivers/gpu/nvgpu/common/acr/acr_gv11b.c
View File

@@ -21,15 +21,15 @@
*/
#include <nvgpu/types.h>
#include <nvgpu/nvgpu_common.h>
#include <nvgpu/firmware.h>
#include <nvgpu/acr/nvgpu_acr.h>
#include <nvgpu/gk20a.h>
#include <nvgpu/bug.h>
#include "pmu_gm20b.h"
#include "common/pmu/pmu_gm20b.h"
#include "acr_gm20b.h"
#include "acr_gp106.h"
#include "acr_gv100.h"
#include "acr_gv11b.h"
static int gv11b_acr_patch_wpr_info_to_ucode(struct gk20a *g,
@@ -86,7 +86,7 @@ static u32 gv11b_acr_lsf_pmu(struct gk20a *g,
lsf->falcon_dma_idx = GK20A_PMU_DMAIDX_UCODE;
lsf->is_lazy_bootstrap = false;
lsf->is_priv_load = false;
lsf->get_lsf_ucode_details = NULL;
lsf->get_lsf_ucode_details = nvgpu_acr_lsf_pmu_ucode_details_v1;
lsf->get_cmd_line_args_offset = nvgpu_pmu_get_cmd_line_args_offset;
return BIT32(lsf->falcon_id);
@@ -101,7 +101,7 @@ static u32 gv11b_acr_lsf_fecs(struct gk20a *g,
lsf->falcon_dma_idx = GK20A_PMU_DMAIDX_UCODE;
lsf->is_lazy_bootstrap = true;
lsf->is_priv_load = false;
lsf->get_lsf_ucode_details = NULL;
lsf->get_lsf_ucode_details = nvgpu_acr_lsf_fecs_ucode_details_v1;
lsf->get_cmd_line_args_offset = NULL;
return BIT32(lsf->falcon_id);
@@ -115,7 +115,7 @@ static u32 gv11b_acr_lsf_gpccs(struct gk20a *g,
lsf->falcon_dma_idx = GK20A_PMU_DMAIDX_UCODE;
lsf->is_lazy_bootstrap = true;
lsf->is_priv_load = true;
lsf->get_lsf_ucode_details = NULL;
lsf->get_lsf_ucode_details = nvgpu_acr_lsf_gpccs_ucode_details_v1;
lsf->get_cmd_line_args_offset = NULL;
return BIT32(lsf->falcon_id);
@@ -159,19 +159,18 @@ void nvgpu_gv11b_acr_sw_init(struct gk20a *g, struct nvgpu_acr *acr)
acr->g = g;
acr->bootstrap_owner = FALCON_ID_PMU;
acr->max_supported_lsfm = MAX_SUPPORTED_LSFM;
acr->lsf_enable_mask = gv11b_acr_lsf_conifg(g, acr);
gv11b_acr_default_sw_init(g, &acr->acr);
acr->prepare_ucode_blob = gp106_prepare_ucode_blob;
acr->get_wpr_info = gm20b_wpr_info;
acr->alloc_blob_space = gm20b_alloc_blob_space;
acr->bootstrap_hs_acr = gm20b_bootstrap_hs_acr;
acr->prepare_ucode_blob = nvgpu_acr_prepare_ucode_blob_v1;
acr->get_wpr_info = nvgpu_acr_wpr_info_sys;
acr->alloc_blob_space = nvgpu_acr_alloc_blob_space_sys;
acr->bootstrap_hs_acr = nvgpu_acr_bootstrap_hs_ucode;
acr->patch_wpr_info_to_ucode = gv11b_acr_patch_wpr_info_to_ucode;
acr->acr_fill_bl_dmem_desc =
gp106_acr_fill_bl_dmem_desc;
gv100_acr_fill_bl_dmem_desc;
acr->remove_support = gm20b_remove_acr_support;
}

0
drivers/gpu/nvgpu/common/pmu/acr_gv11b.h → drivers/gpu/nvgpu/common/acr/acr_gv11b.h
View File

21
drivers/gpu/nvgpu/common/pmu/acr_tu104.c → drivers/gpu/nvgpu/common/acr/acr_tu104.c
View File

@@ -23,20 +23,18 @@
#include <nvgpu/acr/nvgpu_acr.h>
#include <nvgpu/firmware.h>
#include <nvgpu/enabled.h>
#include <nvgpu/utils.h>
#include <nvgpu/debug.h>
#include <nvgpu/kmem.h>
#include <nvgpu/pmu.h>
#include <nvgpu/dma.h>
#include <nvgpu/gk20a.h>
#include <nvgpu/sec2if/sec2_if_cmn.h>
#include "acr_gm20b.h"
#include "acr_gv100.h"
#include "acr_tu104.h"
#include "gv100/gsp_gv100.h"
#include "tu104/sec2_tu104.h"
#include "acr_gm20b.h"
#include "acr_gp106.h"
#include "acr_tu104.h"
static int tu104_bootstrap_hs_acr(struct gk20a *g, struct nvgpu_acr *acr,
struct hs_acr *acr_type)
@@ -45,12 +43,12 @@ static int tu104_bootstrap_hs_acr(struct gk20a *g, struct nvgpu_acr *acr,
nvgpu_log_fn(g, " ");
err = gm20b_bootstrap_hs_acr(g, &g->acr, &g->acr.acr_ahesasc);
err = nvgpu_acr_bootstrap_hs_ucode(g, &g->acr, &g->acr.acr_ahesasc);
if (err != 0) {
nvgpu_err(g, "ACR AHESASC bootstrap failed");
goto exit;
}
err = gm20b_bootstrap_hs_acr(g, &g->acr, &g->acr.acr_asb);
err = nvgpu_acr_bootstrap_hs_ucode(g, &g->acr, &g->acr.acr_asb);
if (err != 0) {
nvgpu_err(g, "ACR ASB bootstrap failed");
goto exit;
@@ -69,7 +67,7 @@ static u32 tu104_acr_lsf_sec2(struct gk20a *g,
lsf->falcon_dma_idx = NV_SEC2_DMAIDX_UCODE;
lsf->is_lazy_bootstrap = false;
lsf->is_priv_load = false;
lsf->get_lsf_ucode_details = NULL;
lsf->get_lsf_ucode_details = nvgpu_acr_lsf_sec2_ucode_details_v1;
lsf->get_cmd_line_args_offset = NULL;
return BIT32(lsf->falcon_id);
@@ -159,14 +157,13 @@ void nvgpu_tu104_acr_sw_init(struct gk20a *g, struct nvgpu_acr *acr)
nvgpu_log_fn(g, " ");
/* Inherit settings from older chip */
nvgpu_gp106_acr_sw_init(g, acr);
nvgpu_gv100_acr_sw_init(g, acr);
acr->lsf_enable_mask |= tu104_acr_lsf_sec2(g,
&acr->lsf[FALCON_ID_SEC2]);
acr->prepare_ucode_blob = gp106_prepare_ucode_blob;
acr->prepare_ucode_blob = nvgpu_acr_prepare_ucode_blob_v1;
acr->bootstrap_owner = FALCON_ID_GSPLITE;
acr->max_supported_lsfm = TU104_MAX_SUPPORTED_LSFM;
acr->bootstrap_hs_acr = tu104_bootstrap_hs_acr;
acr->remove_support = tu104_remove_acr_support;

2
drivers/gpu/nvgpu/common/pmu/acr_tu104.h → drivers/gpu/nvgpu/common/acr/acr_tu104.h
View File

@@ -23,8 +23,6 @@
#ifndef NVGPU_ACR_TU104_H
#define NVGPU_ACR_TU104_H
#define TU104_MAX_SUPPORTED_LSFM 4
#define TU104_FECS_UCODE_SIG "tu104/fecs_sig.bin"
#define TU104_GPCCS_UCODE_SIG "tu104/gpccs_sig.bin"

65
drivers/gpu/nvgpu/common/pmu/acr_gp106.h
View File

@@ -1,65 +0,0 @@
/*
* Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef NVGPU_ACR_GP106_H
#define NVGPU_ACR_GP106_H
int gp106_bootstrap_hs_flcn(struct gk20a *g);
int gp106_prepare_ucode_blob(struct gk20a *g);
int gp106_alloc_blob_space(struct gk20a *g,
size_t size, struct nvgpu_mem *mem);
void gp106_wpr_info(struct gk20a *g, struct wpr_carveout_info *inf);
void lsfm_free_ucode_img_res(struct gk20a *g,
struct flcn_ucode_img_v1 *p_img);
void lsfm_free_nonpmu_ucode_img_res(struct gk20a *g,
struct flcn_ucode_img_v1 *p_img);
int lsf_gen_wpr_requirements(struct gk20a *g,
struct ls_flcn_mgr_v1 *plsfm);
void free_acr_resources(struct gk20a *g, struct ls_flcn_mgr_v1 *plsfm);
void lsfm_fill_static_lsb_hdr_info(struct gk20a *g,
u32 falcon_id, struct lsfm_managed_ucode_img_v2 *pnode);
int pmu_ucode_details(struct gk20a *g, struct flcn_ucode_img_v1 *p_img);
int fecs_ucode_details(struct gk20a *g,
struct flcn_ucode_img_v1 *p_img);
int gpccs_ucode_details(struct gk20a *g,
struct flcn_ucode_img_v1 *p_img);
int sec2_ucode_details(struct gk20a *g, struct flcn_ucode_img_v1 *p_img);
int lsfm_add_ucode_img(struct gk20a *g, struct ls_flcn_mgr_v1 *plsfm,
struct flcn_ucode_img_v1 *ucode_image, u32 falcon_id);
int lsfm_discover_ucode_images(struct gk20a *g,
struct ls_flcn_mgr_v1 *plsfm);
void lsfm_init_wpr_contents(struct gk20a *g,
struct ls_flcn_mgr_v1 *plsfm, struct nvgpu_mem *ucode);
int lsfm_fill_flcn_bl_gen_desc(struct gk20a *g,
struct lsfm_managed_ucode_img_v2 *pnode);
int gp106_acr_fill_bl_dmem_desc(struct gk20a *g,
struct nvgpu_acr *acr, struct hs_acr *acr_desc,
u32 *acr_ucode_header);
int gp106_acr_patch_wpr_info_to_ucode(struct gk20a *g, struct nvgpu_acr *acr,
struct hs_acr *acr_desc, bool is_recovery);
void nvgpu_gp106_acr_sw_init(struct gk20a *g, struct nvgpu_acr *acr);
#endif /* NVGPU_ACR_GP106_H */

1
drivers/gpu/nvgpu/common/pmu/pmu_gm20b.c
View File

@@ -30,7 +30,6 @@
#include <nvgpu/gk20a.h>
#include "pmu_gk20a.h"
#include "acr_gm20b.h"
#include "pmu_gm20b.h"
#include <nvgpu/hw/gm20b/hw_gr_gm20b.h>

3
drivers/gpu/nvgpu/common/pmu/pmu_gp106.c
View File

@@ -28,12 +28,9 @@
#include <nvgpu/pmu/lpwr.h>
#include "pmu_gk20a.h"
#include "acr_gm20b.h"
#include "pmu_gm20b.h"
#include "pmu_gp10b.h"
#include "pmu_gp106.h"
#include "acr_gp106.h"
#include <nvgpu/hw/gp106/hw_psec_gp106.h>
#include <nvgpu/hw/gp106/hw_pwr_gp106.h>

1
drivers/gpu/nvgpu/common/pmu/pmu_gp10b.c
View File

@@ -29,7 +29,6 @@
#include <nvgpu/io.h>
#include <nvgpu/gk20a.h>
#include "acr_gm20b.h"
#include "pmu_gk20a.h"
#include "pmu_gm20b.h"
#include "pmu_gp10b.h"

2
drivers/gpu/nvgpu/common/pmu/pmu_gv11b.c
View File

@@ -35,8 +35,6 @@
#include "pmu_gp10b.h"
#include "pmu_gp106.h"
#include "pmu_gv11b.h"
#include "acr_gv11b.h"
#include <nvgpu/hw/gv11b/hw_pwr_gv11b.h>
#define gv11b_dbg_pmu(g, fmt, arg...) \

2
drivers/gpu/nvgpu/gm20b/hal_gm20b.c
View File

@@ -52,7 +52,7 @@
#include "common/perf/perf_gm20b.h"
#include "common/pmu/pmu_gk20a.h"
#include "common/pmu/pmu_gm20b.h"
#include "common/pmu/acr_gm20b.h"
#include "common/acr/acr_gm20b.h"
#include "common/falcon/falcon_gk20a.h"
#include "common/top/top_gm20b.h"
#include "common/sync/syncpt_cmdbuf_gk20a.h"

3
drivers/gpu/nvgpu/gp10b/hal_gp10b.c
View File

@@ -62,8 +62,7 @@
#include "common/pmu/pmu_gk20a.h"
#include "common/pmu/pmu_gm20b.h"
#include "common/pmu/pmu_gp10b.h"
#include "common/pmu/acr_gm20b.h"
#include "common/pmu/acr_gp10b.h"
#include "common/acr/acr_gp10b.h"
#include "common/falcon/falcon_gk20a.h"
#include "common/top/top_gm20b.h"
#include "common/top/top_gp10b.h"

5
drivers/gpu/nvgpu/gv100/hal_gv100.c
View File

@@ -62,10 +62,9 @@
#include "common/pmu/pmu_gm20b.h"
#include "common/pmu/pmu_gp10b.h"
#include "common/pmu/pmu_gp106.h"
#include "common/pmu/acr_gm20b.h"
#include "common/pmu/acr_gp106.h"
#include "common/pmu/pmu_gv11b.h"
#include "common/pmu/pmu_gv100.h"
#include "common/acr/acr_gv100.h"
#include "common/falcon/falcon_gk20a.h"
#include "common/falcon/falcon_gv100.h"
#include "common/nvdec/nvdec_gp106.h"
@@ -1140,7 +1139,7 @@ static const struct gpu_ops gv100_ops = {
gm20b_top_get_max_tpc_per_gpc_count,
},
.acr = {
.acr_sw_init = nvgpu_gp106_acr_sw_init,
.acr_sw_init = nvgpu_gv100_acr_sw_init,
},
.sec2 = {
.falcon_base_addr = gp106_sec2_falcon_base_addr,

4
drivers/gpu/nvgpu/gv11b/hal_gv11b.c
View File

@@ -57,9 +57,7 @@
#include "common/pmu/pmu_gp10b.h"
#include "common/pmu/pmu_gp106.h"
#include "common/pmu/pmu_gv11b.h"
#include "common/pmu/acr_gm20b.h"
#include "common/pmu/acr_gp106.h"
#include "common/pmu/acr_gv11b.h"
#include "common/acr/acr_gv11b.h"
#include "common/falcon/falcon_gk20a.h"
#include "common/top/top_gm20b.h"
#include "common/top/top_gp10b.h"

34
drivers/gpu/nvgpu/include/nvgpu/acr/nvgpu_acr.h
View File

@@ -45,14 +45,18 @@ struct nvgpu_acr;
#define HSBIN_ACR_AHESASC_DBG_UCODE "acr_ahesasc_dbg_ucode.bin"
#define HSBIN_ACR_ASB_DBG_UCODE "acr_asb_dbg_ucode.bin"
#define GM20B_FECS_UCODE_SIG "fecs_sig.bin"
#define T18x_GPCCS_UCODE_SIG "gpccs_sig.bin"
#define LSF_SEC2_UCODE_IMAGE_BIN "sec2_ucode_image.bin"
#define LSF_SEC2_UCODE_DESC_BIN "sec2_ucode_desc.bin"
#define LSF_SEC2_UCODE_SIG_BIN "sec2_sig.bin"
#define MAX_SUPPORTED_LSFM 3U /*PMU, FECS, GPCCS*/
#define ACR_COMPLETION_TIMEOUT_MS 10000U /*in msec */
#define nvgpu_acr_dbg(g, fmt, args...) \
nvgpu_log(g, gpu_dbg_pmu, fmt, ##args)
struct bin_hdr {
/* 0x10de */
u32 bin_magic;
@@ -99,8 +103,7 @@ struct acr_lsf_config {
bool is_lazy_bootstrap;
bool is_priv_load;
int (*get_lsf_ucode_details)(struct gk20a *g, struct nvgpu_acr *acr,
struct flcn_ucode_img_v1 *udata);
int (*get_lsf_ucode_details)(struct gk20a *g, void *lsf_ucode_img);
void (*get_cmd_line_args_offset)(struct gk20a *g, u32 *args_offset);
};
@@ -152,7 +155,6 @@ struct nvgpu_acr {
struct gk20a *g;
u32 bootstrap_owner;
u32 max_supported_lsfm;
u32 lsf_enable_mask;
struct acr_lsf_config lsf[FALCON_ID_END];
@@ -190,5 +192,27 @@ struct nvgpu_acr {
void (*remove_support)(struct nvgpu_acr *acr);
};
int nvgpu_acr_bootstrap_hs_ucode(struct gk20a *g, struct nvgpu_acr *acr,
struct hs_acr *acr_desc);
int nvgpu_acr_alloc_blob_space_sys(struct gk20a *g, size_t size,
struct nvgpu_mem *mem);
int nvgpu_acr_alloc_blob_space_vid(struct gk20a *g, size_t size,
struct nvgpu_mem *mem);
void nvgpu_acr_wpr_info_sys(struct gk20a *g, struct wpr_carveout_info *inf);
void nvgpu_acr_wpr_info_vid(struct gk20a *g, struct wpr_carveout_info *inf);
int nvgpu_acr_prepare_ucode_blob_v0(struct gk20a *g);
int nvgpu_acr_prepare_ucode_blob_v1(struct gk20a *g);
int nvgpu_acr_lsf_pmu_ucode_details_v0(struct gk20a *g, void *lsf_ucode_img);
int nvgpu_acr_lsf_fecs_ucode_details_v0(struct gk20a *g, void *lsf_ucode_img);
int nvgpu_acr_lsf_gpccs_ucode_details_v0(struct gk20a *g, void *lsf_ucode_img);
int nvgpu_acr_lsf_pmu_ucode_details_v1(struct gk20a *g, void *lsf_ucode_img);
int nvgpu_acr_lsf_fecs_ucode_details_v1(struct gk20a *g, void *lsf_ucode_img);
int nvgpu_acr_lsf_gpccs_ucode_details_v1(struct gk20a *g, void *lsf_ucode_img);
int nvgpu_acr_lsf_sec2_ucode_details_v1(struct gk20a *g, void *lsf_ucode_img);
#endif /* NVGPU_ACR_H */

4
drivers/gpu/nvgpu/tu104/hal_tu104.c
View File

@@ -66,10 +66,8 @@
#include "common/pmu/pmu_gv100.h"
#include "common/pmu/pmu_gv11b.h"
#include "common/pmu/pmu_tu104.h"
#include "common/pmu/acr_gm20b.h"
#include "common/pmu/acr_gp106.h"
#include "common/pmu/acr_tu104.h"
#include "common/pmu/perf/perf_tu104.h"
#include "common/acr/acr_tu104.h"
#include "common/falcon/falcon_gk20a.h"
#include "common/falcon/falcon_tu104.h"
#include "common/nvdec/nvdec_tu104.h"