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gpu: nvgpu: ACR refactor to create ACR unit
Move ACR code to separate folder under common/acr to make ACR separate unit. with this, separating ACR blob construct, bootstrap & ACR chip specific configuration code to different files. ACR blob construction code split into two version, as gm20b & gp10b still uses older ACR interfaces & not yet moved to Tegra ACR, blob_construct_v0 file can be deleted once gm20b/gp10b uses Tegra ACR ucode & point to blob_construct_v1 with simple change. As ACR ucode can execute on different engine falcon & should not be dependent on specific engine falcon, used generic falcon functions/interface to support ACR & doesn't access any engine h/w registers directly, and files with chip name has configuration needed for ACR HS ucode & LS falcons. JIRA NVGPU-1148 Change-Id: Ieedbe82f3e1a4303f055fbc795d9ce0f1866d259 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2017046 GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Mahantesh Kumbar
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commit
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/*
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* GM20B ACR
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*
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* Copyright (c) 2015-2018, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
|
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* copy of this software and associated documentation files (the "Software"),
|
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* to deal in the Software without restriction, including without limitation
|
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
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* and/or sell copies of the Software, and to permit persons to whom the
|
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* Software is furnished to do so, subject to the following conditions:
|
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*
|
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* The above copyright notice and this permission notice shall be included in
|
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef NVGPU_GM20B_ACR_GM20B_H
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#define NVGPU_GM20B_ACR_GM20B_H
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#define GM20B_FECS_UCODE_SIG "fecs_sig.bin"
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#define T18x_GPCCS_UCODE_SIG "gpccs_sig.bin"
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int prepare_ucode_blob(struct gk20a *g);
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int acr_ucode_patch_sig(struct gk20a *g,
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unsigned int *p_img,
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unsigned int *p_prod_sig,
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unsigned int *p_dbg_sig,
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unsigned int *p_patch_loc,
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unsigned int *p_patch_ind);
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int gm20b_alloc_blob_space(struct gk20a *g,
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size_t size, struct nvgpu_mem *mem);
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void gm20b_wpr_info(struct gk20a *g, struct wpr_carveout_info *inf);
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int gm20b_acr_patch_wpr_info_to_ucode(struct gk20a *g,
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struct nvgpu_acr *acr, struct hs_acr *acr_desc, bool is_recovery);
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int gm20b_acr_fill_bl_dmem_desc(struct gk20a *g,
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struct nvgpu_acr *acr, struct hs_acr *acr_desc,
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u32 *acr_ucode_header);
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int gm20b_bootstrap_hs_acr(struct gk20a *g, struct nvgpu_acr *acr,
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struct hs_acr *acr_desc);
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void gm20b_remove_acr_support(struct nvgpu_acr *acr);
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void nvgpu_gm20b_acr_sw_init(struct gk20a *g, struct nvgpu_acr *acr);
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#endif /*NVGPU_GM20B_ACR_GM20B_H*/
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/*
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* Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef NVGPU_ACR_GP106_H
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#define NVGPU_ACR_GP106_H
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int gp106_bootstrap_hs_flcn(struct gk20a *g);
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int gp106_prepare_ucode_blob(struct gk20a *g);
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int gp106_alloc_blob_space(struct gk20a *g,
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size_t size, struct nvgpu_mem *mem);
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void gp106_wpr_info(struct gk20a *g, struct wpr_carveout_info *inf);
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void lsfm_free_ucode_img_res(struct gk20a *g,
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struct flcn_ucode_img_v1 *p_img);
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void lsfm_free_nonpmu_ucode_img_res(struct gk20a *g,
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struct flcn_ucode_img_v1 *p_img);
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int lsf_gen_wpr_requirements(struct gk20a *g,
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struct ls_flcn_mgr_v1 *plsfm);
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void free_acr_resources(struct gk20a *g, struct ls_flcn_mgr_v1 *plsfm);
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void lsfm_fill_static_lsb_hdr_info(struct gk20a *g,
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u32 falcon_id, struct lsfm_managed_ucode_img_v2 *pnode);
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int pmu_ucode_details(struct gk20a *g, struct flcn_ucode_img_v1 *p_img);
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int fecs_ucode_details(struct gk20a *g,
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struct flcn_ucode_img_v1 *p_img);
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int gpccs_ucode_details(struct gk20a *g,
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struct flcn_ucode_img_v1 *p_img);
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int sec2_ucode_details(struct gk20a *g, struct flcn_ucode_img_v1 *p_img);
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int lsfm_add_ucode_img(struct gk20a *g, struct ls_flcn_mgr_v1 *plsfm,
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struct flcn_ucode_img_v1 *ucode_image, u32 falcon_id);
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int lsfm_discover_ucode_images(struct gk20a *g,
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struct ls_flcn_mgr_v1 *plsfm);
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void lsfm_init_wpr_contents(struct gk20a *g,
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struct ls_flcn_mgr_v1 *plsfm, struct nvgpu_mem *ucode);
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int lsfm_fill_flcn_bl_gen_desc(struct gk20a *g,
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struct lsfm_managed_ucode_img_v2 *pnode);
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int gp106_acr_fill_bl_dmem_desc(struct gk20a *g,
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struct nvgpu_acr *acr, struct hs_acr *acr_desc,
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u32 *acr_ucode_header);
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int gp106_acr_patch_wpr_info_to_ucode(struct gk20a *g, struct nvgpu_acr *acr,
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struct hs_acr *acr_desc, bool is_recovery);
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void nvgpu_gp106_acr_sw_init(struct gk20a *g, struct nvgpu_acr *acr);
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#endif /* NVGPU_ACR_GP106_H */
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@@ -1,57 +0,0 @@
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/*
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* Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
|
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
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* and/or sell copies of the Software, and to permit persons to whom the
|
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
|
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/types.h>
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#include <nvgpu/acr/nvgpu_acr.h>
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#include <nvgpu/gk20a.h>
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#include <nvgpu/pmu.h>
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#include "acr_gm20b.h"
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#include "acr_gp10b.h"
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/* LSF static config functions */
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static u32 gp10b_acr_lsf_gpccs(struct gk20a *g,
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struct acr_lsf_config *lsf)
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{
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/* GPCCS LS falcon info */
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lsf->falcon_id = FALCON_ID_GPCCS;
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lsf->falcon_dma_idx = GK20A_PMU_DMAIDX_UCODE;
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lsf->is_lazy_bootstrap = true;
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lsf->is_priv_load = true;
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lsf->get_lsf_ucode_details = NULL;
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lsf->get_cmd_line_args_offset = NULL;
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return BIT32(lsf->falcon_id);
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}
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void nvgpu_gp10b_acr_sw_init(struct gk20a *g, struct nvgpu_acr *acr)
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{
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nvgpu_log_fn(g, " ");
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/* inherit the gm20b config data */
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nvgpu_gm20b_acr_sw_init(g, acr);
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/* gp10b supports LSF gpccs bootstrap */
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acr->lsf_enable_mask |= gp10b_acr_lsf_gpccs(g,
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&acr->lsf[FALCON_ID_GPCCS]);
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}
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@@ -1,28 +0,0 @@
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/*
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* Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
|
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef NVGPU_ACR_GP10B_H
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#define NVGPU_ACR_GP10B_H
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void nvgpu_gp10b_acr_sw_init(struct gk20a *g, struct nvgpu_acr *acr);
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#endif /* NVGPU_ACR_GP10B_H */
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@@ -1,29 +0,0 @@
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/*
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* Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
|
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef NVGPU_ACR_GV100_H
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#define NVGPU_ACR_GV100_H
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#define GV100_FECS_UCODE_SIG "gv100/fecs_sig.bin"
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#define GV100_GPCCS_UCODE_SIG "gv100/gpccs_sig.bin"
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#endif /* NVGPU_ACR_GV100_H */
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@@ -1,177 +0,0 @@
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/*
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* Copyright (c) 2017-2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
|
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* copy of this software and associated documentation files (the "Software"),
|
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* to deal in the Software without restriction, including without limitation
|
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
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* and/or sell copies of the Software, and to permit persons to whom the
|
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
|
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/types.h>
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#include <nvgpu/nvgpu_common.h>
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#include <nvgpu/firmware.h>
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#include <nvgpu/acr/nvgpu_acr.h>
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#include <nvgpu/gk20a.h>
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#include <nvgpu/bug.h>
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#include "pmu_gm20b.h"
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#include "acr_gm20b.h"
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#include "acr_gp106.h"
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#include "acr_gv11b.h"
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static int gv11b_acr_patch_wpr_info_to_ucode(struct gk20a *g,
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struct nvgpu_acr *acr, struct hs_acr *acr_desc, bool is_recovery)
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{
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struct nvgpu_firmware *acr_fw = acr_desc->acr_fw;
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struct acr_fw_header *acr_fw_hdr = NULL;
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struct bin_hdr *acr_fw_bin_hdr = NULL;
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struct flcn_acr_desc_v1 *acr_dmem_desc;
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u32 *acr_ucode_header = NULL;
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u32 *acr_ucode_data = NULL;
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nvgpu_log_fn(g, " ");
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if (is_recovery) {
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acr_desc->acr_dmem_desc_v1->nonwpr_ucode_blob_size = 0U;
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} else {
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acr_fw_bin_hdr = (struct bin_hdr *)acr_fw->data;
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acr_fw_hdr = (struct acr_fw_header *)
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(acr_fw->data + acr_fw_bin_hdr->header_offset);
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acr_ucode_data = (u32 *)(acr_fw->data +
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acr_fw_bin_hdr->data_offset);
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acr_ucode_header = (u32 *)(acr_fw->data +
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acr_fw_hdr->hdr_offset);
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/* During recovery need to update blob size as 0x0*/
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acr_desc->acr_dmem_desc_v1 = (struct flcn_acr_desc_v1 *)
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((u8 *)(acr_desc->acr_ucode.cpu_va) +
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acr_ucode_header[2U]);
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/* Patch WPR info to ucode */
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acr_dmem_desc = (struct flcn_acr_desc_v1 *)
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&(((u8 *)acr_ucode_data)[acr_ucode_header[2U]]);
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acr_dmem_desc->nonwpr_ucode_blob_start =
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nvgpu_mem_get_addr(g, &g->acr.ucode_blob);
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nvgpu_assert(g->acr.ucode_blob.size <= U32_MAX);
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acr_dmem_desc->nonwpr_ucode_blob_size =
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(u32)g->acr.ucode_blob.size;
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acr_dmem_desc->regions.no_regions = 1U;
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acr_dmem_desc->wpr_offset = 0U;
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}
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return 0;
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}
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/* LSF static config functions */
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static u32 gv11b_acr_lsf_pmu(struct gk20a *g,
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struct acr_lsf_config *lsf)
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{
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/* PMU LS falcon info */
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lsf->falcon_id = FALCON_ID_PMU;
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lsf->falcon_dma_idx = GK20A_PMU_DMAIDX_UCODE;
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lsf->is_lazy_bootstrap = false;
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lsf->is_priv_load = false;
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lsf->get_lsf_ucode_details = NULL;
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lsf->get_cmd_line_args_offset = nvgpu_pmu_get_cmd_line_args_offset;
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return BIT32(lsf->falcon_id);
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}
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/* LSF init */
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static u32 gv11b_acr_lsf_fecs(struct gk20a *g,
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struct acr_lsf_config *lsf)
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{
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/* FECS LS falcon info */
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lsf->falcon_id = FALCON_ID_FECS;
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lsf->falcon_dma_idx = GK20A_PMU_DMAIDX_UCODE;
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lsf->is_lazy_bootstrap = true;
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lsf->is_priv_load = false;
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lsf->get_lsf_ucode_details = NULL;
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lsf->get_cmd_line_args_offset = NULL;
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return BIT32(lsf->falcon_id);
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}
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static u32 gv11b_acr_lsf_gpccs(struct gk20a *g,
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struct acr_lsf_config *lsf)
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{
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/* FECS LS falcon info */
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lsf->falcon_id = FALCON_ID_GPCCS;
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lsf->falcon_dma_idx = GK20A_PMU_DMAIDX_UCODE;
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lsf->is_lazy_bootstrap = true;
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lsf->is_priv_load = true;
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lsf->get_lsf_ucode_details = NULL;
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lsf->get_cmd_line_args_offset = NULL;
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return BIT32(lsf->falcon_id);
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}
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static u32 gv11b_acr_lsf_conifg(struct gk20a *g,
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struct nvgpu_acr *acr)
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{
|
||||
u32 lsf_enable_mask = 0;
|
||||
|
||||
lsf_enable_mask |= gv11b_acr_lsf_pmu(g, &acr->lsf[FALCON_ID_PMU]);
|
||||
lsf_enable_mask |= gv11b_acr_lsf_fecs(g, &acr->lsf[FALCON_ID_FECS]);
|
||||
lsf_enable_mask |= gv11b_acr_lsf_gpccs(g, &acr->lsf[FALCON_ID_GPCCS]);
|
||||
|
||||
return lsf_enable_mask;
|
||||
}
|
||||
|
||||
static void gv11b_acr_default_sw_init(struct gk20a *g, struct hs_acr *hs_acr)
|
||||
{
|
||||
struct hs_flcn_bl *hs_bl = &hs_acr->acr_hs_bl;
|
||||
|
||||
nvgpu_log_fn(g, " ");
|
||||
|
||||
hs_bl->bl_fw_name = HSBIN_ACR_BL_UCODE_IMAGE;
|
||||
|
||||
hs_acr->acr_type = ACR_DEFAULT;
|
||||
hs_acr->acr_fw_name = HSBIN_ACR_UCODE_IMAGE;
|
||||
|
||||
hs_acr->ptr_bl_dmem_desc = &hs_acr->bl_dmem_desc_v1;
|
||||
hs_acr->bl_dmem_desc_size = (u32)sizeof(struct flcn_bl_dmem_desc_v1);
|
||||
|
||||
hs_acr->acr_flcn = g->pmu.flcn;
|
||||
hs_acr->acr_flcn_setup_hw_and_bl_bootstrap =
|
||||
gm20b_pmu_setup_hw_and_bl_bootstrap;
|
||||
}
|
||||
|
||||
void nvgpu_gv11b_acr_sw_init(struct gk20a *g, struct nvgpu_acr *acr)
|
||||
{
|
||||
nvgpu_log_fn(g, " ");
|
||||
|
||||
acr->g = g;
|
||||
|
||||
acr->bootstrap_owner = FALCON_ID_PMU;
|
||||
acr->max_supported_lsfm = MAX_SUPPORTED_LSFM;
|
||||
|
||||
acr->lsf_enable_mask = gv11b_acr_lsf_conifg(g, acr);
|
||||
|
||||
gv11b_acr_default_sw_init(g, &acr->acr);
|
||||
|
||||
acr->prepare_ucode_blob = gp106_prepare_ucode_blob;
|
||||
acr->get_wpr_info = gm20b_wpr_info;
|
||||
acr->alloc_blob_space = gm20b_alloc_blob_space;
|
||||
acr->bootstrap_hs_acr = gm20b_bootstrap_hs_acr;
|
||||
acr->patch_wpr_info_to_ucode = gv11b_acr_patch_wpr_info_to_ucode;
|
||||
acr->acr_fill_bl_dmem_desc =
|
||||
gp106_acr_fill_bl_dmem_desc;
|
||||
|
||||
acr->remove_support = gm20b_remove_acr_support;
|
||||
}
|
||||
@@ -1,29 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef NVGPU_ACR_GV11B_H
|
||||
#define NVGPU_ACR_GV11B_H
|
||||
|
||||
void nvgpu_gv11b_acr_sw_init(struct gk20a *g, struct nvgpu_acr *acr);
|
||||
|
||||
#endif /* NVGPU_ACR_GV11B_H */
|
||||
|
||||
@@ -1,178 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#include <nvgpu/acr/nvgpu_acr.h>
|
||||
#include <nvgpu/firmware.h>
|
||||
#include <nvgpu/enabled.h>
|
||||
#include <nvgpu/utils.h>
|
||||
#include <nvgpu/debug.h>
|
||||
#include <nvgpu/kmem.h>
|
||||
#include <nvgpu/pmu.h>
|
||||
#include <nvgpu/dma.h>
|
||||
#include <nvgpu/gk20a.h>
|
||||
#include <nvgpu/sec2if/sec2_if_cmn.h>
|
||||
|
||||
#include "gv100/gsp_gv100.h"
|
||||
#include "tu104/sec2_tu104.h"
|
||||
|
||||
#include "acr_gm20b.h"
|
||||
#include "acr_gp106.h"
|
||||
#include "acr_tu104.h"
|
||||
|
||||
static int tu104_bootstrap_hs_acr(struct gk20a *g, struct nvgpu_acr *acr,
|
||||
struct hs_acr *acr_type)
|
||||
{
|
||||
int err = 0;
|
||||
|
||||
nvgpu_log_fn(g, " ");
|
||||
|
||||
err = gm20b_bootstrap_hs_acr(g, &g->acr, &g->acr.acr_ahesasc);
|
||||
if (err != 0) {
|
||||
nvgpu_err(g, "ACR AHESASC bootstrap failed");
|
||||
goto exit;
|
||||
}
|
||||
err = gm20b_bootstrap_hs_acr(g, &g->acr, &g->acr.acr_asb);
|
||||
if (err != 0) {
|
||||
nvgpu_err(g, "ACR ASB bootstrap failed");
|
||||
goto exit;
|
||||
}
|
||||
|
||||
exit:
|
||||
return err;
|
||||
}
|
||||
|
||||
/* LSF init */
|
||||
static u32 tu104_acr_lsf_sec2(struct gk20a *g,
|
||||
struct acr_lsf_config *lsf)
|
||||
{
|
||||
/* SEC2 LS falcon info */
|
||||
lsf->falcon_id = FALCON_ID_SEC2;
|
||||
lsf->falcon_dma_idx = NV_SEC2_DMAIDX_UCODE;
|
||||
lsf->is_lazy_bootstrap = false;
|
||||
lsf->is_priv_load = false;
|
||||
lsf->get_lsf_ucode_details = NULL;
|
||||
lsf->get_cmd_line_args_offset = NULL;
|
||||
|
||||
return BIT32(lsf->falcon_id);
|
||||
}
|
||||
|
||||
/* ACR-AHESASC(ACR hub encryption setter and signature checker) init*/
|
||||
static void nvgpu_tu104_acr_ahesasc_sw_init(struct gk20a *g,
|
||||
struct hs_acr *acr_ahesasc)
|
||||
{
|
||||
struct hs_flcn_bl *hs_bl = &acr_ahesasc->acr_hs_bl;
|
||||
|
||||
hs_bl->bl_fw_name = HSBIN_ACR_BL_UCODE_IMAGE;
|
||||
|
||||
acr_ahesasc->acr_type = ACR_AHESASC;
|
||||
|
||||
if (!g->ops.pmu.is_debug_mode_enabled(g)) {
|
||||
acr_ahesasc->acr_fw_name = HSBIN_ACR_AHESASC_PROD_UCODE;
|
||||
} else {
|
||||
acr_ahesasc->acr_fw_name = HSBIN_ACR_AHESASC_DBG_UCODE;
|
||||
}
|
||||
|
||||
acr_ahesasc->ptr_bl_dmem_desc = &acr_ahesasc->bl_dmem_desc_v1;
|
||||
acr_ahesasc->bl_dmem_desc_size = (u32)sizeof(struct flcn_bl_dmem_desc_v1);
|
||||
|
||||
acr_ahesasc->acr_flcn = g->sec2.flcn;
|
||||
acr_ahesasc->acr_flcn_setup_hw_and_bl_bootstrap =
|
||||
tu104_sec2_setup_hw_and_bl_bootstrap;
|
||||
}
|
||||
|
||||
/* ACR-ASB(ACR SEC2 booter) init*/
|
||||
static void nvgpu_tu104_acr_asb_sw_init(struct gk20a *g,
|
||||
struct hs_acr *acr_asb)
|
||||
{
|
||||
struct hs_flcn_bl *hs_bl = &acr_asb->acr_hs_bl;
|
||||
|
||||
hs_bl->bl_fw_name = HSBIN_ACR_BL_UCODE_IMAGE;
|
||||
|
||||
acr_asb->acr_type = ACR_ASB;
|
||||
|
||||
if (!g->ops.pmu.is_debug_mode_enabled(g)) {
|
||||
acr_asb->acr_fw_name = HSBIN_ACR_ASB_PROD_UCODE;
|
||||
} else {
|
||||
acr_asb->acr_fw_name = HSBIN_ACR_ASB_DBG_UCODE;
|
||||
}
|
||||
|
||||
acr_asb->ptr_bl_dmem_desc = &acr_asb->bl_dmem_desc_v1;
|
||||
acr_asb->bl_dmem_desc_size = (u32)sizeof(struct flcn_bl_dmem_desc_v1);
|
||||
|
||||
acr_asb->acr_flcn = g->gsp_flcn;
|
||||
acr_asb->acr_flcn_setup_hw_and_bl_bootstrap =
|
||||
gv100_gsp_setup_hw_and_bl_bootstrap;
|
||||
}
|
||||
|
||||
static void tu104_free_hs_acr(struct gk20a *g,
|
||||
struct hs_acr *acr_type)
|
||||
{
|
||||
struct mm_gk20a *mm = &g->mm;
|
||||
struct vm_gk20a *vm = mm->pmu.vm;
|
||||
|
||||
if (acr_type->acr_fw != NULL) {
|
||||
nvgpu_release_firmware(g, acr_type->acr_fw);
|
||||
}
|
||||
|
||||
if (acr_type->acr_hs_bl.hs_bl_fw != NULL) {
|
||||
nvgpu_release_firmware(g, acr_type->acr_hs_bl.hs_bl_fw);
|
||||
}
|
||||
|
||||
if (nvgpu_mem_is_valid(&acr_type->acr_ucode)) {
|
||||
nvgpu_dma_unmap_free(vm, &acr_type->acr_ucode);
|
||||
}
|
||||
if (nvgpu_mem_is_valid(&acr_type->acr_hs_bl.hs_bl_ucode)) {
|
||||
nvgpu_dma_unmap_free(vm, &acr_type->acr_hs_bl.hs_bl_ucode);
|
||||
}
|
||||
}
|
||||
|
||||
static void tu104_remove_acr_support(struct nvgpu_acr *acr)
|
||||
{
|
||||
struct gk20a *g = acr->g;
|
||||
|
||||
tu104_free_hs_acr(g, &acr->acr_ahesasc);
|
||||
|
||||
tu104_free_hs_acr(g, &acr->acr_asb);
|
||||
}
|
||||
|
||||
void nvgpu_tu104_acr_sw_init(struct gk20a *g, struct nvgpu_acr *acr)
|
||||
{
|
||||
nvgpu_log_fn(g, " ");
|
||||
|
||||
/* Inherit settings from older chip */
|
||||
nvgpu_gp106_acr_sw_init(g, acr);
|
||||
|
||||
acr->lsf_enable_mask |= tu104_acr_lsf_sec2(g,
|
||||
&acr->lsf[FALCON_ID_SEC2]);
|
||||
|
||||
acr->prepare_ucode_blob = gp106_prepare_ucode_blob;
|
||||
acr->bootstrap_owner = FALCON_ID_GSPLITE;
|
||||
acr->max_supported_lsfm = TU104_MAX_SUPPORTED_LSFM;
|
||||
acr->bootstrap_hs_acr = tu104_bootstrap_hs_acr;
|
||||
acr->remove_support = tu104_remove_acr_support;
|
||||
|
||||
/* Init ACR-AHESASC */
|
||||
nvgpu_tu104_acr_ahesasc_sw_init(g, &acr->acr_ahesasc);
|
||||
|
||||
/* Init ACR-ASB*/
|
||||
nvgpu_tu104_acr_asb_sw_init(g, &acr->acr_asb);
|
||||
}
|
||||
@@ -1,33 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef NVGPU_ACR_TU104_H
|
||||
#define NVGPU_ACR_TU104_H
|
||||
|
||||
#define TU104_MAX_SUPPORTED_LSFM 4
|
||||
|
||||
#define TU104_FECS_UCODE_SIG "tu104/fecs_sig.bin"
|
||||
#define TU104_GPCCS_UCODE_SIG "tu104/gpccs_sig.bin"
|
||||
|
||||
void nvgpu_tu104_acr_sw_init(struct gk20a *g, struct nvgpu_acr *acr);
|
||||
|
||||
#endif /*NVGPU_ACR_TU104_H*/
|
||||
@@ -30,7 +30,6 @@
|
||||
#include <nvgpu/gk20a.h>
|
||||
|
||||
#include "pmu_gk20a.h"
|
||||
#include "acr_gm20b.h"
|
||||
#include "pmu_gm20b.h"
|
||||
|
||||
#include <nvgpu/hw/gm20b/hw_gr_gm20b.h>
|
||||
|
||||
@@ -28,12 +28,9 @@
|
||||
#include <nvgpu/pmu/lpwr.h>
|
||||
|
||||
#include "pmu_gk20a.h"
|
||||
#include "acr_gm20b.h"
|
||||
#include "pmu_gm20b.h"
|
||||
#include "pmu_gp10b.h"
|
||||
#include "pmu_gp106.h"
|
||||
#include "acr_gp106.h"
|
||||
|
||||
#include <nvgpu/hw/gp106/hw_psec_gp106.h>
|
||||
#include <nvgpu/hw/gp106/hw_pwr_gp106.h>
|
||||
|
||||
|
||||
@@ -29,7 +29,6 @@
|
||||
#include <nvgpu/io.h>
|
||||
#include <nvgpu/gk20a.h>
|
||||
|
||||
#include "acr_gm20b.h"
|
||||
#include "pmu_gk20a.h"
|
||||
#include "pmu_gm20b.h"
|
||||
#include "pmu_gp10b.h"
|
||||
|
||||
@@ -35,8 +35,6 @@
|
||||
#include "pmu_gp10b.h"
|
||||
#include "pmu_gp106.h"
|
||||
#include "pmu_gv11b.h"
|
||||
#include "acr_gv11b.h"
|
||||
|
||||
#include <nvgpu/hw/gv11b/hw_pwr_gv11b.h>
|
||||
|
||||
#define gv11b_dbg_pmu(g, fmt, arg...) \
|
||||
|
||||
Reference in New Issue
Block a user