gpu: nvgpu: add gops.fifo.setup_sw

bar1/userd setup is different for RM server. created common function
gk20a_init_fifo_setup_sw_common.

Jira VQRM-3058

Change-Id: I655b54e21ed5f15dcb8e7b01bd9cd129b35ae7a3
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1665691
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

drivers/gpu/nvgpu/gk20a/fifo_gk20a.c

@@ -862,24 +862,27 @@ int gk20a_init_fifo_reset_enable_hw(struct gk20a *g)
 	return 0;
 }
 
-int gk20a_init_fifo_setup_sw(struct gk20a *g)
+int gk20a_init_fifo_setup_sw_common(struct gk20a *g)
 {
 	struct fifo_gk20a *f = &g->fifo;
 	unsigned int chid, i;
 	int err = 0;
-	u64 userd_base;
 
 	gk20a_dbg_fn("");
 
-	if (f->sw_ready) {
-		gk20a_dbg_fn("skip init");
-		return 0;
-	}
-
 	f->g = g;
 
-	nvgpu_mutex_init(&f->intr.isr.mutex);
-	nvgpu_mutex_init(&f->gr_reset_mutex);
+	err = nvgpu_mutex_init(&f->intr.isr.mutex);
+	if (err) {
+		nvgpu_err(g, "failed to init isr.mutex");
+		return err;
+	}
+
+	err = nvgpu_mutex_init(&f->gr_reset_mutex);
+	if (err) {
+		nvgpu_err(g, "failed to init gr_reset_mutex");
+		return err;
+	}
 
 	g->ops.fifo.init_pbdma_intr_descs(f); /* just filling in data/tables */
 
@@ -914,7 +917,73 @@ int gk20a_init_fifo_setup_sw(struct gk20a *g)
 	init_runlist(g, f);
 
 	nvgpu_init_list_node(&f->free_chs);
-	nvgpu_mutex_init(&f->free_chs_mutex);
+
+	err = nvgpu_mutex_init(&f->free_chs_mutex);
+	if (err) {
+		nvgpu_err(g, "failed to init free_chs_mutex");
+		goto clean_up;
+	}
+
+	for (chid = 0; chid < f->num_channels; chid++) {
+		gk20a_init_channel_support(g, chid);
+		gk20a_init_tsg_support(g, chid);
+	}
+
+	err = nvgpu_mutex_init(&f->tsg_inuse_mutex);
+	if (err) {
+		nvgpu_err(g, "failed to init tsg_inuse_mutex");
+		goto clean_up;
+	}
+
+	f->remove_support = gk20a_remove_fifo_support;
+
+	f->deferred_reset_pending = false;
+
+	err = nvgpu_mutex_init(&f->deferred_reset_mutex);
+	if (err) {
+		nvgpu_err(g, "failed to init deferred_reset_mutex");
+		goto clean_up;
+	}
+
+	gk20a_dbg_fn("done");
+	return 0;
+
+clean_up:
+	nvgpu_err(g, "fail");
+
+	nvgpu_vfree(g, f->channel);
+	f->channel = NULL;
+	nvgpu_vfree(g, f->tsg);
+	f->tsg = NULL;
+	nvgpu_kfree(g, f->pbdma_map);
+	f->pbdma_map = NULL;
+	nvgpu_kfree(g, f->engine_info);
+	f->engine_info = NULL;
+	nvgpu_kfree(g, f->active_engines_list);
+	f->active_engines_list = NULL;
+
+	return err;
+}
+
+int gk20a_init_fifo_setup_sw(struct gk20a *g)
+{
+	struct fifo_gk20a *f = &g->fifo;
+	unsigned int chid;
+	u64 userd_base;
+	int err = 0;
+
+	gk20a_dbg_fn("");
+
+	if (f->sw_ready) {
+		gk20a_dbg_fn("skip init");
+		return 0;
+	}
+
+	err = gk20a_init_fifo_setup_sw_common(g);
+	if (err) {
+		nvgpu_err(g, "fail: err: %d", err);
+		return err;
+	}
 
 	if (g->ops.mm.is_bar1_supported(g))
 		err = nvgpu_dma_alloc_map_sys(g->mm.bar1.vm,
@@ -936,18 +1005,11 @@ int gk20a_init_fifo_setup_sw(struct gk20a *g)
 			chid * f->userd_entry_size;
 		f->channel[chid].userd_gpu_va =
 			f->userd.gpu_va + chid * f->userd_entry_size;
-		gk20a_init_channel_support(g, chid);
-		gk20a_init_tsg_support(g, chid);
 	}
-	nvgpu_mutex_init(&f->tsg_inuse_mutex);
 
 	err = nvgpu_channel_worker_init(g);
 	if (err)
 		goto clean_up;
-	f->remove_support = gk20a_remove_fifo_support;
-
-	f->deferred_reset_pending = false;
-	nvgpu_mutex_init(&f->deferred_reset_mutex);
 
 	f->sw_ready = true;
 
@@ -956,21 +1018,12 @@ int gk20a_init_fifo_setup_sw(struct gk20a *g)
 
 clean_up:
 	gk20a_dbg_fn("fail");
-	if (g->ops.mm.is_bar1_supported(g))
-		nvgpu_dma_unmap_free(g->mm.bar1.vm, &f->userd);
-	else
-		nvgpu_dma_free(g, &f->userd);
-
-	nvgpu_vfree(g, f->channel);
-	f->channel = NULL;
-	nvgpu_vfree(g, f->tsg);
-	f->tsg = NULL;
-	nvgpu_kfree(g, f->pbdma_map);
-	f->pbdma_map = NULL;
-	nvgpu_kfree(g, f->engine_info);
-	f->engine_info = NULL;
-	nvgpu_kfree(g, f->active_engines_list);
-	f->active_engines_list = NULL;
+	if (nvgpu_mem_is_valid(&f->userd)) {
+		if (g->ops.mm.is_bar1_supported(g))
+			nvgpu_dma_unmap_free(g->mm.bar1.vm, &f->userd);
+		else
+			nvgpu_dma_free(g, &f->userd);
+	}
 
 	return err;
 }
@@ -1049,7 +1102,7 @@ int gk20a_init_fifo_support(struct gk20a *g)
 {
 	u32 err;
 
-	err = gk20a_init_fifo_setup_sw(g);
+	err = g->ops.fifo.setup_sw(g);
 	if (err)
 		return err;
 

drivers/gpu/nvgpu/gk20a/fifo_gk20a.h

@@ -386,6 +386,7 @@ u32 *gk20a_runlist_construct_locked(struct fifo_gk20a *f,
 				bool prev_empty,
 				u32 *entries_left);
 int gk20a_fifo_runlist_wait_pending(struct gk20a *g, u32 runlist_id);
+int gk20a_init_fifo_setup_sw_common(struct gk20a *g);
 int gk20a_init_fifo_setup_sw(struct gk20a *g);
 void gk20a_fifo_handle_runlist_event(struct gk20a *g);
 bool gk20a_fifo_should_defer_engine_reset(struct gk20a *g, u32 engine_id,

drivers/gpu/nvgpu/gk20a/gk20a.h

@@ -532,6 +532,7 @@ struct gpu_ops {
 		void (*post_events)(struct channel_gk20a *ch);
 	} debugger;
 	struct {
+		int (*setup_sw)(struct gk20a *g);
 		int (*init_fifo_setup_hw)(struct gk20a *g);
 		void (*bind_channel)(struct channel_gk20a *ch_gk20a);
 		void (*unbind_channel)(struct channel_gk20a *ch_gk20a);

drivers/gpu/nvgpu/gm20b/hal_gm20b.c

@@ -445,6 +445,7 @@ static const struct gpu_ops gm20b_ops = {
 		.channel_suspend = gk20a_channel_suspend,
 		.channel_resume = gk20a_channel_resume,
 		.set_error_notifier = nvgpu_set_error_notifier,
+		.setup_sw = gk20a_init_fifo_setup_sw,
 #ifdef CONFIG_TEGRA_GK20A_NVHOST
 		.alloc_syncpt_buf = gk20a_fifo_alloc_syncpt_buf,
 		.free_syncpt_buf = gk20a_fifo_free_syncpt_buf,

drivers/gpu/nvgpu/gp106/hal_gp106.c

@@ -506,6 +506,7 @@ static const struct gpu_ops gp106_ops = {
 		.channel_suspend = gk20a_channel_suspend,
 		.channel_resume = gk20a_channel_resume,
 		.set_error_notifier = nvgpu_set_error_notifier,
+		.setup_sw = gk20a_init_fifo_setup_sw,
 #ifdef CONFIG_TEGRA_GK20A_NVHOST
 		.alloc_syncpt_buf = gk20a_fifo_alloc_syncpt_buf,
 		.free_syncpt_buf = gk20a_fifo_free_syncpt_buf,

drivers/gpu/nvgpu/gp10b/hal_gp10b.c

@@ -477,6 +477,7 @@ static const struct gpu_ops gp10b_ops = {
 		.channel_suspend = gk20a_channel_suspend,
 		.channel_resume = gk20a_channel_resume,
 		.set_error_notifier = nvgpu_set_error_notifier,
+		.setup_sw = gk20a_init_fifo_setup_sw,
 #ifdef CONFIG_TEGRA_GK20A_NVHOST
 		.alloc_syncpt_buf = gk20a_fifo_alloc_syncpt_buf,
 		.free_syncpt_buf = gk20a_fifo_free_syncpt_buf,

drivers/gpu/nvgpu/gv100/hal_gv100.c

@@ -518,6 +518,7 @@ static const struct gpu_ops gv100_ops = {
 		.channel_suspend = gk20a_channel_suspend,
 		.channel_resume = gk20a_channel_resume,
 		.set_error_notifier = nvgpu_set_error_notifier,
+		.setup_sw = gk20a_init_fifo_setup_sw,
 #ifdef CONFIG_TEGRA_GK20A_NVHOST
 		.alloc_syncpt_buf = gv11b_fifo_alloc_syncpt_buf,
 		.free_syncpt_buf = gv11b_fifo_free_syncpt_buf,

drivers/gpu/nvgpu/gv11b/hal_gv11b.c

@@ -535,6 +535,7 @@ static const struct gpu_ops gv11b_ops = {
 		.channel_suspend = gk20a_channel_suspend,
 		.channel_resume = gk20a_channel_resume,
 		.set_error_notifier = nvgpu_set_error_notifier,
+		.setup_sw = gk20a_init_fifo_setup_sw,
 #ifdef CONFIG_TEGRA_GK20A_NVHOST
 		.alloc_syncpt_buf = gv11b_fifo_alloc_syncpt_buf,
 		.free_syncpt_buf = gv11b_fifo_free_syncpt_buf,

drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c

@@ -351,6 +351,7 @@ static const struct gpu_ops vgpu_gp10b_ops = {
 		.channel_suspend = gk20a_channel_suspend,
 		.channel_resume = gk20a_channel_resume,
 		.set_error_notifier = nvgpu_set_error_notifier,
+		.setup_sw = gk20a_init_fifo_setup_sw,
 #ifdef CONFIG_TEGRA_GK20A_NVHOST
 		.alloc_syncpt_buf = gk20a_fifo_alloc_syncpt_buf,
 		.free_syncpt_buf = gk20a_fifo_free_syncpt_buf,

drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c

@@ -394,6 +394,7 @@ static const struct gpu_ops vgpu_gv11b_ops = {
 		.channel_suspend = gk20a_channel_suspend,
 		.channel_resume = gk20a_channel_resume,
 		.set_error_notifier = nvgpu_set_error_notifier,
+		.setup_sw = gk20a_init_fifo_setup_sw,
 #ifdef CONFIG_TEGRA_GK20A_NVHOST
 		.alloc_syncpt_buf = vgpu_gv11b_fifo_alloc_syncpt_buf,
 		.free_syncpt_buf = gv11b_fifo_free_syncpt_buf,