gpu: nvgpu: pmu version update

- ucode CL http://git-master/r/#/c/935012/
- EXTERR exception for ZBC L2 regsiters access
  during ELPG entry/exit.
  FIX : ZBC L2 is not part of GR, so ZBC L2 rigsters
  save/restore not required for ELPG entry/exit,
  P4 CL 20360931
- 10 msec as GR_FECS_SUBMIT_METHOD_TIMEOUT_US, P4 CL 20313730
- keep disabled ELCG till Clear DAT_RESTORE
  interrupt at ELPG exit path, P4 CL 20313676

 Bug 1712507
 Bug 200166877

Change-Id: I2c9843cfd18cd3b513ee6587d1a79e7034b19cae
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/935019
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
This commit is contained in:
Mahantesh Kumbar
2016-01-20 15:18:04 +05:30
committed by Terje Bergstrom
parent f28526bb72
commit 0bade2cb45
2 changed files with 6 additions and 6 deletions

View File

@@ -1,7 +1,7 @@
/*
* GK20A PMU (aka. gPMU outside gk20a context)
*
* Copyright (c) 2011-2015, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2011-2016, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
@@ -1005,8 +1005,8 @@ int gk20a_init_pmu(struct pmu_gk20a *pmu)
pmu->remove_support = gk20a_remove_pmu_support;
switch (pmu->desc->app_version) {
case APP_VERSION_T186_1:
case APP_VERSION_T186_0:
case APP_VERSION_NC_1:
case APP_VERSION_NC_0:
g->ops.pmu_ver.pg_cmd_eng_buf_load_size =
pg_cmd_eng_buf_load_size_v1;
g->ops.pmu_ver.pg_cmd_eng_buf_load_set_cmd_type =

View File

@@ -3,7 +3,7 @@
*
* GK20A PMU (aka. gPMU outside gk20a context)
*
* Copyright (c) 2011-2015, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2011-2016, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
@@ -49,8 +49,8 @@
/* Mapping between AP_CTRLs and Idle counters */
#define PMU_AP_IDLE_MASK_GRAPHICS (PMU_AP_IDLE_MASK_HIST_IDX_1)
#define APP_VERSION_T186_1 19870492
#define APP_VERSION_T186_0 20120791
#define APP_VERSION_NC_1 20313802
#define APP_VERSION_NC_0 20120791
#define APP_VERSION_GM20B_4 19008461
#define APP_VERSION_GM20B_3 18935575
#define APP_VERSION_GM20B_2 18694072