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gpu: nvgpu: Fix misra 4.7 errors in gr ecc unit

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Fix misra 4.7 violations in gr ecc unit
misra_c_2012_directive_4_7_violation: return error information hasn't been tested.

jira NVGPU-4054

Change-Id: I6e10a637f45886667de733827444526216061cc7
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2197398
Reviewed-by: Prateek Sethi <prsethi@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Vinod G
2019-09-13 12:59:35 -07:00
committed by Alex Waterman
parent ca39cacdaf
commit 0deeb6b2f8
3 changed files with 35 additions and 105 deletions
Download Patch File Download Diff File Expand all files Collapse all files

69
drivers/gpu/nvgpu/hal/gr/ecc/ecc_gp10b.c
View File

@@ -126,66 +126,27 @@ void gp10b_ecc_detect_enabled_units(struct gk20a *g)
static int gp10b_ecc_init_tpc_sm(struct gk20a *g)
{
int err = 0;
NVGPU_ECC_COUNTER_INIT_PER_TPC(sm_lrf_ecc_single_err_count);
NVGPU_ECC_COUNTER_INIT_PER_TPC(sm_lrf_ecc_double_err_count);
NVGPU_ECC_COUNTER_INIT_PER_TPC(sm_shm_ecc_sec_count);
NVGPU_ECC_COUNTER_INIT_PER_TPC(sm_shm_ecc_sed_count);
NVGPU_ECC_COUNTER_INIT_PER_TPC(sm_shm_ecc_ded_count);
err = NVGPU_ECC_COUNTER_INIT_PER_TPC(sm_lrf_ecc_single_err_count);
if (err != 0) {
goto init_tpc_sm_err;
}
err = NVGPU_ECC_COUNTER_INIT_PER_TPC(sm_lrf_ecc_double_err_count);
if (err != 0) {
goto init_tpc_sm_err;
}
err = NVGPU_ECC_COUNTER_INIT_PER_TPC(sm_shm_ecc_sec_count);
if (err != 0) {
goto init_tpc_sm_err;
}
err = NVGPU_ECC_COUNTER_INIT_PER_TPC(sm_shm_ecc_sed_count);
if (err != 0) {
goto init_tpc_sm_err;
}
err = NVGPU_ECC_COUNTER_INIT_PER_TPC(sm_shm_ecc_ded_count);
init_tpc_sm_err:
return err;
return 0;
}
static int gp10b_ecc_init_tpc_tex(struct gk20a *g)
{
int err = 0;
NVGPU_ECC_COUNTER_INIT_PER_TPC(tex_ecc_total_sec_pipe0_count);
NVGPU_ECC_COUNTER_INIT_PER_TPC(tex_ecc_total_ded_pipe0_count);
NVGPU_ECC_COUNTER_INIT_PER_TPC(tex_unique_ecc_sec_pipe0_count);
NVGPU_ECC_COUNTER_INIT_PER_TPC(tex_unique_ecc_ded_pipe0_count);
NVGPU_ECC_COUNTER_INIT_PER_TPC(tex_ecc_total_sec_pipe1_count);
NVGPU_ECC_COUNTER_INIT_PER_TPC(tex_ecc_total_ded_pipe1_count);
NVGPU_ECC_COUNTER_INIT_PER_TPC(tex_unique_ecc_sec_pipe1_count);
NVGPU_ECC_COUNTER_INIT_PER_TPC(tex_unique_ecc_ded_pipe1_count);
err = NVGPU_ECC_COUNTER_INIT_PER_TPC(tex_ecc_total_sec_pipe0_count);
if (err != 0) {
goto init_tpc_tex_err;
}
err = NVGPU_ECC_COUNTER_INIT_PER_TPC(tex_ecc_total_ded_pipe0_count);
if (err != 0) {
goto init_tpc_tex_err;
}
err = NVGPU_ECC_COUNTER_INIT_PER_TPC(tex_unique_ecc_sec_pipe0_count);
if (err != 0) {
goto init_tpc_tex_err;
}
err = NVGPU_ECC_COUNTER_INIT_PER_TPC(tex_unique_ecc_ded_pipe0_count);
if (err != 0) {
goto init_tpc_tex_err;
}
err = NVGPU_ECC_COUNTER_INIT_PER_TPC(tex_ecc_total_sec_pipe1_count);
if (err != 0) {
goto init_tpc_tex_err;
}
err = NVGPU_ECC_COUNTER_INIT_PER_TPC(tex_ecc_total_ded_pipe1_count);
if (err != 0) {
goto init_tpc_tex_err;
}
err = NVGPU_ECC_COUNTER_INIT_PER_TPC(tex_unique_ecc_sec_pipe1_count);
if (err != 0) {
goto init_tpc_tex_err;
}
err = NVGPU_ECC_COUNTER_INIT_PER_TPC(tex_unique_ecc_ded_pipe1_count);
init_tpc_tex_err:
return err;
return 0;
}
static int gp10b_ecc_init_tpc(struct gk20a *g)

60
drivers/gpu/nvgpu/hal/gr/ecc/ecc_gv11b_fusa.c
View File

@@ -482,56 +482,18 @@ void gv11b_ecc_detect_enabled_units(struct gk20a *g)
static int gv11b_ecc_init_tpc(struct gk20a *g)
{
int err = 0;
NVGPU_ECC_COUNTER_INIT_PER_TPC(sm_lrf_ecc_single_err_count);
NVGPU_ECC_COUNTER_INIT_PER_TPC(sm_lrf_ecc_double_err_count);
NVGPU_ECC_COUNTER_INIT_PER_TPC(sm_l1_tag_ecc_corrected_err_count);
NVGPU_ECC_COUNTER_INIT_PER_TPC(sm_l1_tag_ecc_uncorrected_err_count);
NVGPU_ECC_COUNTER_INIT_PER_TPC(sm_cbu_ecc_corrected_err_count);
NVGPU_ECC_COUNTER_INIT_PER_TPC(sm_cbu_ecc_uncorrected_err_count);
NVGPU_ECC_COUNTER_INIT_PER_TPC(sm_l1_data_ecc_corrected_err_count);
NVGPU_ECC_COUNTER_INIT_PER_TPC(sm_l1_data_ecc_uncorrected_err_count);
NVGPU_ECC_COUNTER_INIT_PER_TPC(sm_icache_ecc_corrected_err_count);
NVGPU_ECC_COUNTER_INIT_PER_TPC(sm_icache_ecc_uncorrected_err_count);
err = NVGPU_ECC_COUNTER_INIT_PER_TPC(sm_lrf_ecc_single_err_count);
if (err != 0) {
goto init_tpc_done;
}
err = NVGPU_ECC_COUNTER_INIT_PER_TPC(sm_lrf_ecc_double_err_count);
if (err != 0) {
goto init_tpc_done;
}
err = NVGPU_ECC_COUNTER_INIT_PER_TPC(
sm_l1_tag_ecc_corrected_err_count);
if (err != 0) {
goto init_tpc_done;
}
err = NVGPU_ECC_COUNTER_INIT_PER_TPC(
sm_l1_tag_ecc_uncorrected_err_count);
if (err != 0) {
goto init_tpc_done;
}
err = NVGPU_ECC_COUNTER_INIT_PER_TPC(
sm_cbu_ecc_corrected_err_count);
if (err != 0) {
goto init_tpc_done;
}
err = NVGPU_ECC_COUNTER_INIT_PER_TPC(
sm_cbu_ecc_uncorrected_err_count);
if (err != 0) {
goto init_tpc_done;
}
err = NVGPU_ECC_COUNTER_INIT_PER_TPC(
sm_l1_data_ecc_corrected_err_count);
if (err != 0) {
goto init_tpc_done;
}
err = NVGPU_ECC_COUNTER_INIT_PER_TPC(
sm_l1_data_ecc_uncorrected_err_count);
if (err != 0) {
goto init_tpc_done;
}
err = NVGPU_ECC_COUNTER_INIT_PER_TPC(
sm_icache_ecc_corrected_err_count);
if (err != 0) {
goto init_tpc_done;
}
err = NVGPU_ECC_COUNTER_INIT_PER_TPC(
sm_icache_ecc_uncorrected_err_count);
init_tpc_done:
return err;
return 0;
}
static int gv11b_ecc_init_gpc(struct gk20a *g)

11
drivers/gpu/nvgpu/include/nvgpu/ecc.h
View File

@@ -123,8 +123,15 @@ struct nvgpu_ecc {
int nvgpu_ecc_counter_init_per_tpc(struct gk20a *g,
struct nvgpu_ecc_stat ***stat, const char *name);
#define NVGPU_ECC_COUNTER_INIT_PER_TPC(stat) \
nvgpu_ecc_counter_init_per_tpc(g, &g->ecc.gr.stat, #stat)
#define NVGPU_ECC_COUNTER_INIT_PER_TPC(stat) \
do { \
int err = 0; \
err = nvgpu_ecc_counter_init_per_tpc(g, \
&g->ecc.gr.stat, #stat);\
if (err != 0) { \
return err; \
} \
} while (false)
int nvgpu_ecc_counter_init_per_gpc(struct gk20a *g,
struct nvgpu_ecc_stat **stat, const char *name);