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gpu: nvgpu: write with ack for mailbox1 during fecs trace
FECS ucode does a priv holdoff around the assertion of context reset. So, priv transactions (e.g. mailbox1 register write) might fail due to this. Hence, do write with ack i.e. write and read it back to make sure write happened for mailbox1. Bug 200417403 Change-Id: I463be1cb8fdd477106b87786cb0603327a22cebe Signed-off-by: Vaibhav Kachore <vkachore@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2023494 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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@@ -266,6 +266,17 @@ int gk20a_fecs_trace_poll(struct gk20a *g)
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nvgpu_wmb();
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gk20a_fecs_trace_set_read_index(g, read);
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/*
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* FECS ucode does a priv holdoff around the assertion of context
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* reset. So, pri transactions (e.g. mailbox1 register write) might
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* fail due to this. Hence, do write with ack i.e. write and read
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* it back to make sure write happened for mailbox1.
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*/
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while (gk20a_fecs_trace_get_read_index(g) != read) {
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nvgpu_log(g, gpu_dbg_ctxsw, "mailbox1 update failed");
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gk20a_fecs_trace_set_read_index(g, read);
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}
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done:
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nvgpu_mutex_release(&trace->poll_lock);
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gk20a_idle(g);
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