gpu: nvgpu: Add multi GR sec2 boot support

This CL covers the following code changes,
1) Added API to get the physical gpc id masks.
2) Added multi GR instance sec2 boot support for MIG.

JIRA NVGPU-5650

Change-Id: I16c6bd34b5e8d86ad807fafac4b2441c097eb3e2
Signed-off-by: Lakshmanan M <lm@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2419092
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
This commit is contained in:
Lakshmanan M
2020-09-24 15:31:04 +05:30
committed by Alex Waterman
parent 673cd507a8
commit 0e7b6e27e8
3 changed files with 50 additions and 7 deletions

View File

@@ -473,3 +473,30 @@ u32 nvgpu_grmgr_get_gr_max_veid_count(struct gk20a *g, u32 gr_instance_id)
return nvgpu_grmgr_get_max_veid_count(g, gpu_instance_id);
}
u32 nvgpu_grmgr_get_gr_physical_gpc_mask(struct gk20a *g, u32 gr_instance_id)
{
u32 physical_gpc_mask = 0U;
u32 gpc_indx;
struct nvgpu_gpu_instance *gpu_instance;
struct nvgpu_gr_syspipe *gr_syspipe;
u32 gpu_instance_id = nvgpu_grmgr_get_gpu_instance_id(
g, gr_instance_id);
gpu_instance = &g->mig.gpu_instance[gpu_instance_id];
gr_syspipe = &gpu_instance->gr_syspipe;
for (gpc_indx = 0U; gpc_indx < gr_syspipe->num_gpc; gpc_indx++) {
physical_gpc_mask |= BIT32(
gr_syspipe->gpcs[gpc_indx].physical_id);
nvgpu_log(g, gpu_dbg_mig,
"gpu_instance_id[%u] gr_instance_id[%u] gpc_indx[%u] "
"physical_gpc_id[%u] physical_gpc_mask[%x]",
gpu_instance_id, gr_instance_id, gpc_indx,
gr_syspipe->gpcs[gpc_indx].physical_id,
physical_gpc_mask);
}
return physical_gpc_mask;
}