gpu: nvgpu: add common.gr.setup unit

Add new unit common.gr.setup that provides runtime setup interfaces to
other units outside of GR unit or to OS-specific code

Move zcull setup call to this unit.
New unit now exposes nvgpu_gr_setup_bind_ctxsw_zcull() to setup zcull
This API internally calls common.gr.zcull API nvgpu_gr_zcull_ctx_setup()

Add new hal g->ops.gr.setup.bind_ctxsw_zcull() and remove
g->ops.gr.zcull.bind_ctxsw_zcull()

Remove nvgpu_channel_gr_zcull_setup() from channel unit
Also remove ctx/subctx header includes sicne channel code need not
configure zcull

Remove gm20b_gr_bind_ctxsw_zcull() since binding is done from common
code

Jira NVGPU-1886

Change-Id: I6f04d19a8b8c003734702c5f6780a03ffc89b717
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2086602
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

drivers/gpu/nvgpu/Makefile

@@ -80,6 +80,7 @@ nvgpu-y += \
 	common/gr/gr_config.o \
 	common/gr/fecs_trace.o \
 	common/gr/zbc.o \
+	common/gr/gr_setup.o \
 	common/gr/hwpm_map.o \
 	common/netlist/netlist.o \
 	common/netlist/netlist_sim.o \

drivers/gpu/nvgpu/Makefile.sources

@@ -115,6 +115,7 @@ srcs += common/sim.c \
 	common/gr/gr_config.c \
 	common/gr/fecs_trace.c \
 	common/gr/zbc.c \
+	common/gr/gr_setup.c \
 	common/gr/hwpm_map.c \
 	common/netlist/netlist.c \
 	common/netlist/netlist_sim.c \

drivers/gpu/nvgpu/common/fifo/channel.c

@@ -44,8 +44,6 @@
 #include <nvgpu/log2.h>
 #include <nvgpu/ptimer.h>
 #include <nvgpu/gk20a.h>
-#include <nvgpu/gr/ctx.h>
-#include <nvgpu/gr/subctx.h>
 #include <nvgpu/gr/gr.h>
 #include <nvgpu/channel.h>
 #include <nvgpu/channel_sync.h>
@@ -217,23 +215,6 @@ void gk20a_channel_abort_clean_up(struct channel_gk20a *ch)
 	gk20a_channel_update(ch);
 }
 
-int nvgpu_channel_gr_zcull_setup(struct gk20a *g, struct channel_gk20a *c,
-			struct nvgpu_gr_ctx *gr_ctx)
-{
-	int ret = 0;
-
-	if (c->subctx != NULL) {
-		ret = nvgpu_gr_ctx_zcull_setup(g, gr_ctx, false);
-		if (ret == 0) {
-			nvgpu_gr_subctx_zcull_setup(g, c->subctx, gr_ctx);
-		}
-	} else {
-		ret = nvgpu_gr_ctx_zcull_setup(g, gr_ctx, true);
-	}
-
-	return ret;
-}
-
 void gk20a_channel_set_unserviceable(struct channel_gk20a *ch)
 {
 	nvgpu_spinlock_acquire(&ch->unserviceable_lock);

drivers/gpu/nvgpu/common/gr/gr_setup.c

@@ -0,0 +1,80 @@
+/*
+ * Copyright (c) 2019, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <nvgpu/log.h>
+#include <nvgpu/gk20a.h>
+#include <nvgpu/gr/ctx.h>
+#include <nvgpu/gr/zcull.h>
+#include <nvgpu/gr/setup.h>
+#include <nvgpu/channel.h>
+
+static int nvgpu_gr_setup_zcull(struct gk20a *g, struct channel_gk20a *c,
+				struct nvgpu_gr_ctx *gr_ctx)
+{
+	int ret = 0;
+
+	nvgpu_log_fn(g, " ");
+
+	ret = gk20a_disable_channel_tsg(g, c);
+	if (ret != 0) {
+		nvgpu_err(g, "failed to disable channel/TSG");
+		return ret;
+	}
+
+	ret = gk20a_fifo_preempt(g, c);
+	if (ret != 0) {
+		if (gk20a_enable_channel_tsg(g, c) != 0) {
+			nvgpu_err(g, "failed to re-enable channel/TSG");
+		}
+		nvgpu_err(g, "failed to preempt channel/TSG");
+		return ret;
+	}
+
+	ret = nvgpu_gr_zcull_ctx_setup(g, c->subctx, gr_ctx);
+	if (ret != 0) {
+		nvgpu_err(g, "failed to setup zcull");
+	}
+
+	ret = gk20a_enable_channel_tsg(g, c);
+	if (ret != 0) {
+		nvgpu_err(g, "failed to enable channel/TSG");
+	}
+
+	return ret;
+}
+
+int nvgpu_gr_setup_bind_ctxsw_zcull(struct gk20a *g, struct channel_gk20a *c,
+			u64 zcull_va, u32 mode)
+{
+	struct tsg_gk20a *tsg;
+	struct nvgpu_gr_ctx *gr_ctx;
+
+	tsg = tsg_gk20a_from_ch(c);
+	if (tsg == NULL) {
+		return -EINVAL;
+	}
+
+	gr_ctx = tsg->gr_ctx;
+	nvgpu_gr_ctx_set_zcull_ctx(g, gr_ctx, mode, zcull_va);
+
+	return nvgpu_gr_setup_zcull(g, c, gr_ctx);
+}

drivers/gpu/nvgpu/common/gr/zcull.c

@@ -143,3 +143,21 @@ int nvgpu_gr_zcull_init_hw(struct gk20a *g,
 
 	return 0;
 }
+
+int nvgpu_gr_zcull_ctx_setup(struct gk20a *g, struct nvgpu_gr_subctx *subctx,
+		struct nvgpu_gr_ctx *gr_ctx)
+{
+	int ret = 0;
+
+	if (subctx != NULL) {
+		ret = nvgpu_gr_ctx_zcull_setup(g, gr_ctx, false);
+		if (ret == 0) {
+			nvgpu_gr_subctx_zcull_setup(g, subctx, gr_ctx);
+		}
+	} else {
+		ret = nvgpu_gr_ctx_zcull_setup(g, gr_ctx, true);
+	}
+
+	return ret;
+}
+

drivers/gpu/nvgpu/common/vgpu/gp10b/vgpu_hal_gp10b.c

@@ -273,6 +273,9 @@ static const struct gpu_ops vgpu_gp10b_ops = {
 			.get_gpc_tpc_mask = vgpu_gr_get_gpc_tpc_mask,
 			.init_sm_id_table = vgpu_gr_init_sm_id_table,
 		},
+		.setup = {
+			.bind_ctxsw_zcull = vgpu_gr_bind_ctxsw_zcull,
+		},
 		.zbc = {
 			.add_color = NULL,
 			.add_depth = NULL,
@@ -283,7 +286,6 @@ static const struct gpu_ops vgpu_gp10b_ops = {
 			.get_gpcs_swdx_dss_zbc_z_format_reg = NULL,
 		},
 		.zcull = {
-			.bind_ctxsw_zcull = vgpu_gr_bind_ctxsw_zcull,
 			.get_zcull_info = vgpu_gr_get_zcull_info,
 			.program_zcull_mapping = NULL,
 		},

drivers/gpu/nvgpu/common/vgpu/gv11b/vgpu_hal_gv11b.c

@@ -320,6 +320,9 @@ static const struct gpu_ops vgpu_gv11b_ops = {
 			.get_gpc_tpc_mask = vgpu_gr_get_gpc_tpc_mask,
 			.init_sm_id_table = vgpu_gr_init_sm_id_table,
 		},
+		.setup = {
+			.bind_ctxsw_zcull = vgpu_gr_bind_ctxsw_zcull,
+		},
 		.zbc = {
 			.add_color = NULL,
 			.add_depth = NULL,
@@ -330,7 +333,6 @@ static const struct gpu_ops vgpu_gv11b_ops = {
 			.get_gpcs_swdx_dss_zbc_z_format_reg = NULL,
 		},
 		.zcull = {
-			.bind_ctxsw_zcull = vgpu_gr_bind_ctxsw_zcull,
 			.get_zcull_info = vgpu_gr_get_zcull_info,
 			.program_zcull_mapping = NULL,
 		},

drivers/gpu/nvgpu/gm20b/hal_gm20b.c

@@ -39,6 +39,7 @@
 #include <nvgpu/gr/zbc.h>
 #include <nvgpu/gr/zcull.h>
 #include <nvgpu/gr/gr_falcon.h>
+#include <nvgpu/gr/setup.h>
 
 #include "hal/bus/bus_gm20b.h"
 #include "hal/bus/bus_gk20a.h"
@@ -392,6 +393,9 @@ static const struct gpu_ops gm20b_ops = {
 				gm20b_gr_config_get_pd_dist_skip_table_size,
 			.init_sm_id_table = gm20b_gr_config_init_sm_id_table,
 		},
+		.setup = {
+			.bind_ctxsw_zcull = nvgpu_gr_setup_bind_ctxsw_zcull,
+		},
 		.zbc = {
 			.add_color = gm20b_gr_zbc_add_color,
 			.add_depth = gm20b_gr_zbc_add_depth,
@@ -403,7 +407,6 @@ static const struct gpu_ops gm20b_ops = {
 		},
 		.zcull = {
 			.init_zcull_hw = gm20b_gr_init_zcull_hw,
-			.bind_ctxsw_zcull = gm20b_gr_bind_ctxsw_zcull,
 			.get_zcull_info = gm20b_gr_get_zcull_info,
 			.program_zcull_mapping = gm20b_gr_program_zcull_mapping,
 		},

drivers/gpu/nvgpu/gp10b/hal_gp10b.c

@@ -39,6 +39,7 @@
 #include <nvgpu/gr/zbc.h>
 #include <nvgpu/gr/zcull.h>
 #include <nvgpu/gr/gr_falcon.h>
+#include <nvgpu/gr/setup.h>
 #include <nvgpu/gr/fecs_trace.h>
 
 #include "hal/bus/bus_gk20a.h"
@@ -460,6 +461,9 @@ static const struct gpu_ops gp10b_ops = {
 			.set_read_index = gm20b_fecs_trace_set_read_index,
 		},
 #endif /* CONFIG_GK20A_CTXSW_TRACE */
+		.setup = {
+			.bind_ctxsw_zcull = nvgpu_gr_setup_bind_ctxsw_zcull,
+		},
 		.zbc = {
 			.add_color = gp10b_gr_zbc_add_color,
 			.add_depth = gp10b_gr_zbc_add_depth,
@@ -473,7 +477,6 @@ static const struct gpu_ops gp10b_ops = {
 		},
 		.zcull = {
 			.init_zcull_hw = gm20b_gr_init_zcull_hw,
-			.bind_ctxsw_zcull = gm20b_gr_bind_ctxsw_zcull,
 			.get_zcull_info = gm20b_gr_get_zcull_info,
 			.program_zcull_mapping = gm20b_gr_program_zcull_mapping,
 		},

drivers/gpu/nvgpu/gv100/hal_gv100.c

@@ -168,6 +168,7 @@
 #include <nvgpu/gr/zbc.h>
 #include <nvgpu/gr/zcull.h>
 #include <nvgpu/gr/gr_falcon.h>
+#include <nvgpu/gr/setup.h>
 #include <nvgpu/gr/fecs_trace.h>
 
 #include <nvgpu/hw/gv100/hw_proj_gv100.h>
@@ -595,6 +596,9 @@ static const struct gpu_ops gv100_ops = {
 			.set_read_index = gm20b_fecs_trace_set_read_index,
 		},
 #endif /* CONFIG_GK20A_CTXSW_TRACE */
+		.setup = {
+			.bind_ctxsw_zcull = nvgpu_gr_setup_bind_ctxsw_zcull,
+		},
 		.zbc = {
 			.add_color = gp10b_gr_zbc_add_color,
 			.add_depth = gp10b_gr_zbc_add_depth,
@@ -608,7 +612,6 @@ static const struct gpu_ops gv100_ops = {
 		},
 		.zcull = {
 			.init_zcull_hw = gm20b_gr_init_zcull_hw,
-			.bind_ctxsw_zcull = gm20b_gr_bind_ctxsw_zcull,
 			.get_zcull_info = gm20b_gr_get_zcull_info,
 			.program_zcull_mapping = gv11b_gr_program_zcull_mapping,
 		},

drivers/gpu/nvgpu/gv11b/hal_gv11b.c

@@ -143,6 +143,7 @@
 #include <nvgpu/cyclestats_snapshot.h>
 #include <nvgpu/gr/zbc.h>
 #include <nvgpu/gr/zcull.h>
+#include <nvgpu/gr/setup.h>
 #include <nvgpu/gr/fecs_trace.h>
 
 #include <nvgpu/hw/gv11b/hw_proj_gv11b.h>
@@ -555,6 +556,9 @@ static const struct gpu_ops gv11b_ops = {
 			.set_read_index = gm20b_fecs_trace_set_read_index,
 		},
 #endif /* CONFIG_GK20A_CTXSW_TRACE */
+		.setup = {
+			.bind_ctxsw_zcull = nvgpu_gr_setup_bind_ctxsw_zcull,
+		},
 		.zbc = {
 			.add_color = gp10b_gr_zbc_add_color,
 			.add_depth = gp10b_gr_zbc_add_depth,
@@ -568,7 +572,6 @@ static const struct gpu_ops gv11b_ops = {
 		},
 		.zcull = {
 			.init_zcull_hw = gm20b_gr_init_zcull_hw,
-			.bind_ctxsw_zcull = gm20b_gr_bind_ctxsw_zcull,
 			.get_zcull_info = gm20b_gr_get_zcull_info,
 			.program_zcull_mapping = gv11b_gr_program_zcull_mapping,
 		},

drivers/gpu/nvgpu/hal/gr/zcull/zcull_gm20b.c

@@ -22,7 +22,6 @@
 
 #include <nvgpu/gk20a.h>
 #include <nvgpu/io.h>
-#include <nvgpu/channel.h>
 #include <nvgpu/gr/config.h>
 #include <nvgpu/gr/subctx.h>
 #include <nvgpu/gr/ctx.h>
@@ -275,54 +274,3 @@ void gm20b_gr_program_zcull_mapping(struct gk20a *g, u32 zcull_num_entries,
 
 }
 
-static int gm20b_gr_ctx_zcull_setup(struct gk20a *g, struct channel_gk20a *c,
-				struct nvgpu_gr_ctx *gr_ctx)
-{
-	int ret = 0;
-
-	nvgpu_log_fn(g, " ");
-
-	ret = gk20a_disable_channel_tsg(g, c);
-	if (ret != 0) {
-		nvgpu_err(g, "failed to disable channel/TSG");
-		return ret;
-	}
-	ret = gk20a_fifo_preempt(g, c);
-	if (ret != 0) {
-		if (gk20a_enable_channel_tsg(g, c) != 0) {
-			nvgpu_err(g, "failed to re-enable channel/TSG");
-		}
-		nvgpu_err(g, "failed to preempt channel/TSG");
-		return ret;
-	}
-
-	ret = nvgpu_channel_gr_zcull_setup(g, c, gr_ctx);
-	if (ret != 0) {
-		nvgpu_err(g, "failed to set up zcull");
-	}
-
-	ret = gk20a_enable_channel_tsg(g, c);
-	if (ret != 0) {
-		nvgpu_err(g, "failed to enable channel/TSG");
-	}
-
-	return ret;
-}
-
-int gm20b_gr_bind_ctxsw_zcull(struct gk20a *g, struct channel_gk20a *c,
-			u64 zcull_va, u32 mode)
-{
-	struct tsg_gk20a *tsg;
-	struct nvgpu_gr_ctx *gr_ctx;
-
-	tsg = tsg_gk20a_from_ch(c);
-	if (tsg == NULL) {
-		return -EINVAL;
-	}
-
-	gr_ctx = tsg->gr_ctx;
-	nvgpu_gr_ctx_set_zcull_ctx(g, gr_ctx, mode, zcull_va);
-
-	/* TBD: don't disable channel in sw method processing */
-	return gm20b_gr_ctx_zcull_setup(g, c, gr_ctx);
-}

drivers/gpu/nvgpu/hal/gr/zcull/zcull_gm20b.h

@@ -40,7 +40,5 @@ int gm20b_gr_get_zcull_info(struct gk20a *g,
 			struct nvgpu_gr_zcull_info *zcull_params);
 void gm20b_gr_program_zcull_mapping(struct gk20a *g, u32 zcull_num_entries,
 					u32 *zcull_map_tiles);
-int gm20b_gr_bind_ctxsw_zcull(struct gk20a *g, struct channel_gk20a *c,
-			u64 zcull_va, u32 mode);
 
 #endif /* NVGPU_GR_ZCULL_GM20B_H */

drivers/gpu/nvgpu/include/nvgpu/channel.h

@@ -473,8 +473,6 @@ int nvgpu_submit_channel_gpfifo_kernel(struct channel_gk20a *c,
 				u32 flags,
 				struct nvgpu_channel_fence *fence,
 				struct gk20a_fence **fence_out);
-int nvgpu_channel_gr_zcull_setup(struct gk20a *g, struct channel_gk20a *c,
-			struct nvgpu_gr_ctx *gr_ctx);
 
 #ifdef CONFIG_DEBUG_FS
 void trace_write_pushbuffers(struct channel_gk20a *c, u32 count);

drivers/gpu/nvgpu/include/nvgpu/gk20a.h

@@ -630,6 +630,13 @@ struct gpu_ops {
 		} fecs_trace;
 #endif
 
+		struct {
+			int (*bind_ctxsw_zcull)(struct gk20a *g,
+						struct channel_gk20a *c,
+						u64 zcull_va,
+						u32 mode);
+		} setup;
+
 		struct {
 			int (*add_color)(struct gk20a *g,
 				struct nvgpu_gr_zbc_entry *color_val,
@@ -655,10 +662,6 @@ struct gpu_ops {
 			int (*init_zcull_hw)(struct gk20a *g,
 					struct nvgpu_gr_zcull *gr_zcull,
 					struct nvgpu_gr_config *gr_config);
-			int (*bind_ctxsw_zcull)(struct gk20a *g,
-						struct channel_gk20a *c,
-						u64 zcull_va,
-						u32 mode);
 			int (*get_zcull_info)(struct gk20a *g,
 				struct nvgpu_gr_config *gr_config,
 				struct nvgpu_gr_zcull *gr_zcull,

drivers/gpu/nvgpu/include/nvgpu/gr/setup.h

@@ -0,0 +1,33 @@
+/*
+ * Copyright (c) 2018-2019, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+#ifndef NVGPU_GR_SETUP_H
+#define NVGPU_GR_SETUP_H
+
+#include <nvgpu/types.h>
+
+struct gk20a;
+struct channel_gk20a;
+
+int nvgpu_gr_setup_bind_ctxsw_zcull(struct gk20a *g, struct channel_gk20a *c,
+			u64 zcull_va, u32 mode);
+
+#endif /* NVGPU_GR_SETUP_H */

drivers/gpu/nvgpu/include/nvgpu/gr/zcull.h

@@ -27,6 +27,8 @@
 
 struct gk20a;
 struct nvgpu_gr_config;
+struct nvgpu_gr_ctx;
+struct nvgpu_gr_subctx;
 
 struct nvgpu_gr_zcull {
 	struct gk20a *g;
@@ -65,4 +67,7 @@ int nvgpu_gr_zcull_init_hw(struct gk20a *g,
 			struct nvgpu_gr_zcull *gr_zcull,
 			struct nvgpu_gr_config *gr_config);
 
+int nvgpu_gr_zcull_ctx_setup(struct gk20a *g, struct nvgpu_gr_subctx *subctx,
+		struct nvgpu_gr_ctx *gr_ctx);
+
 #endif /* NVGPU_GR_ZCULL_H */

drivers/gpu/nvgpu/os/linux/ioctl_channel.c

@@ -753,7 +753,7 @@ static int gk20a_channel_zcull_bind(struct channel_gk20a *ch,
 
 	nvgpu_log_fn(gr->g, " ");
 
-	return g->ops.gr.zcull.bind_ctxsw_zcull(g, ch,
+	return g->ops.gr.setup.bind_ctxsw_zcull(g, ch,
 				args->gpu_va, args->mode);
 }
 

drivers/gpu/nvgpu/tu104/hal_tu104.c

@@ -185,6 +185,7 @@
 #include <nvgpu/cyclestats_snapshot.h>
 #include <nvgpu/regops.h>
 #include <nvgpu/gr/zbc.h>
+#include <nvgpu/gr/setup.h>
 #include <nvgpu/gr/fecs_trace.h>
 #include <nvgpu/pmu/perf.h>
 #include <nvgpu/gr/gr_falcon.h>
@@ -623,6 +624,9 @@ static const struct gpu_ops tu104_ops = {
 			.set_read_index = gm20b_fecs_trace_set_read_index,
 		},
 #endif /* CONFIG_GK20A_CTXSW_TRACE */
+		.setup = {
+			.bind_ctxsw_zcull = nvgpu_gr_setup_bind_ctxsw_zcull,
+		},
 		.zbc = {
 			.add_color = gp10b_gr_zbc_add_color,
 			.add_depth = gp10b_gr_zbc_add_depth,
@@ -636,7 +640,6 @@ static const struct gpu_ops tu104_ops = {
 		},
 		.zcull = {
 			.init_zcull_hw = gm20b_gr_init_zcull_hw,
-			.bind_ctxsw_zcull = gm20b_gr_bind_ctxsw_zcull,
 			.get_zcull_info = gm20b_gr_get_zcull_info,
 			.program_zcull_mapping = gv11b_gr_program_zcull_mapping,
 		},