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gpu: nvgpu: add new gr falcon hals related to context

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Added following new hals in gr falcon:
u32 (*get_current_ctx)(struct gk20a *g);
		-> to get current context in execution.
u32 (*get_ctx_ptr)(u32 ctx);
		-> related ctx_ptr for the context

Updated gr_gk20a.c, gr_gm20b.c, gr_gp10b.c and gr_gv11b.c
to use these new hals.

JIRA NVGPU-1881

Change-Id: I1c1cef8e4b0ca04e3e3218d552b6e8e08fcfa7d0
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2087039
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Seshendra Gadagottu
2019-04-01 13:37:45 -07:00
committed by mobile promotions
parent 4b433b528e
commit 0f3117c166
12 changed files with 35 additions and 10 deletions
Download Patch File Download Diff File Expand all files Collapse all files

14
drivers/gpu/nvgpu/gk20a/gr_gk20a.c
View File

@@ -90,7 +90,7 @@ void nvgpu_report_gr_exception(struct gk20a *g, u32 inst,
}
tsgid = NVGPU_INVALID_TSG_ID;
curr_ctx = gk20a_readl(g, gr_fecs_current_ctx_r());
curr_ctx = g->ops.gr.falcon.get_current_ctx(g);
ch = gk20a_gr_get_channel_from_ctx(g, curr_ctx, &tsgid);
chid = ch != NULL ? ch->chid : FIFO_INVAL_CHANNEL_ID;
if (ch != NULL) {
@@ -128,7 +128,7 @@ static void nvgpu_report_gr_sm_exception(struct gk20a *g, u32 gpc, u32 tpc,
}
tsgid = NVGPU_INVALID_TSG_ID;
curr_ctx = gk20a_readl(g, gr_fecs_current_ctx_r());
curr_ctx = g->ops.gr.falcon.get_current_ctx(g);
ch = gk20a_gr_get_channel_from_ctx(g, curr_ctx, &tsgid);
chid = ch != NULL ? ch->chid : FIFO_INVAL_CHANNEL_ID;
if (ch != NULL) {
@@ -162,7 +162,7 @@ static void gr_report_ctxsw_error(struct gk20a *g, u32 err_type, u32 chid,
int ret = 0;
struct ctxsw_err_info err_info;
err_info.curr_ctx = gk20a_readl(g, gr_fecs_current_ctx_r());
err_info.curr_ctx = g->ops.gr.falcon.get_current_ctx(g);
err_info.ctxsw_status0 = gk20a_readl(g, gr_fecs_ctxsw_status_fe_0_r());
err_info.ctxsw_status1 = gk20a_readl(g, gr_fecs_ctxsw_status_1_r());
err_info.mailbox_value = mailbox_value;
@@ -1556,7 +1556,7 @@ int gk20a_gr_handle_notify_pending(struct gk20a *g,
/* Used by sw interrupt thread to translate current ctx to chid.
* Also used by regops to translate current ctx to chid and tsgid.
* For performance, we don't want to go through 128 channels every time.
* curr_ctx should be the value read from gr_fecs_current_ctx_r().
* curr_ctx should be the value read from gr falcon get_current_ctx op
* A small tlb is used here to cache translation.
*
* Returned channel must be freed with gk20a_channel_put() */
@@ -1598,7 +1598,7 @@ static struct channel_gk20a *gk20a_gr_get_channel_from_ctx(
if ((u32)(nvgpu_inst_block_addr(g, &ch->inst_block) >>
ram_in_base_shift_v()) ==
gr_fecs_current_ctx_ptr_v(curr_ctx)) {
g->ops.gr.falcon.get_ctx_ptr(curr_ctx)) {
tsgid = ch->tsgid;
/* found it */
ret = ch;
@@ -1981,7 +1981,7 @@ int gk20a_gr_isr(struct gk20a *g)
isr_data.addr = gk20a_readl(g, gr_trapped_addr_r());
isr_data.data_lo = gk20a_readl(g, gr_trapped_data_lo_r());
isr_data.data_hi = gk20a_readl(g, gr_trapped_data_hi_r());
isr_data.curr_ctx = gk20a_readl(g, gr_fecs_current_ctx_r());
isr_data.curr_ctx = g->ops.gr.falcon.get_current_ctx(g);
isr_data.offset = gr_trapped_addr_mthd_v(isr_data.addr);
isr_data.sub_chan = gr_trapped_addr_subch_v(isr_data.addr);
obj_table = (isr_data.sub_chan < 4U) ? gk20a_readl(g,
@@ -3481,7 +3481,7 @@ bool gk20a_is_channel_ctx_resident(struct channel_gk20a *ch)
bool ret = false;
struct tsg_gk20a *tsg;
curr_gr_ctx = gk20a_readl(g, gr_fecs_current_ctx_r());
curr_gr_ctx = g->ops.gr.falcon.get_current_ctx(g);
/* when contexts are unloaded from GR, the valid bit is reset
* but the instance pointer information remains intact. So the

2
drivers/gpu/nvgpu/gm20b/gr_gm20b.c
View File

@@ -528,7 +528,7 @@ int gr_gm20b_dump_gr_status_regs(struct gk20a *g,
gk20a_debug_output(o, "NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_IDLESTATE : 0x%x\n",
gk20a_readl(g, gr_gpc0_gpccs_ctxsw_idlestate_r()));
gk20a_debug_output(o, "NV_PGRAPH_PRI_FECS_CURRENT_CTX : 0x%x\n",
gk20a_readl(g, gr_fecs_current_ctx_r()));
g->ops.gr.falcon.get_current_ctx(g));
gk20a_debug_output(o, "NV_PGRAPH_PRI_FECS_NEW_CTX : 0x%x\n",
gk20a_readl(g, gr_fecs_new_ctx_r()));
gk20a_debug_output(o, "NV_PGRAPH_PRI_BE0_CROP_STATUS1 : 0x%x\n",

2
drivers/gpu/nvgpu/gm20b/hal_gm20b.c
View File

@@ -528,6 +528,8 @@ static const struct gpu_ops gm20b_ops = {
.halt_pipe = nvgpu_gr_falcon_halt_pipe,
.disable_ctxsw = nvgpu_gr_falcon_disable_ctxsw,
.enable_ctxsw = nvgpu_gr_falcon_enable_ctxsw,
.get_current_ctx = gm20b_gr_falcon_get_current_ctx,
.get_ctx_ptr = gm20b_gr_falcon_get_ctx_ptr,
},
},
.fb = {

2
drivers/gpu/nvgpu/gp10b/gr_gp10b.c
View File

@@ -851,7 +851,7 @@ int gr_gp10b_dump_gr_status_regs(struct gk20a *g,
gk20a_debug_output(o, "NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_IDLESTATE : 0x%x\n",
gk20a_readl(g, gr_gpc0_gpccs_ctxsw_idlestate_r()));
gk20a_debug_output(o, "NV_PGRAPH_PRI_FECS_CURRENT_CTX : 0x%x\n",
gk20a_readl(g, gr_fecs_current_ctx_r()));
g->ops.gr.falcon.get_current_ctx(g));
gk20a_debug_output(o, "NV_PGRAPH_PRI_FECS_NEW_CTX : 0x%x\n",
gk20a_readl(g, gr_fecs_new_ctx_r()));
gk20a_debug_output(o, "NV_PGRAPH_PRI_BE0_CROP_STATUS1 : 0x%x\n",

2
drivers/gpu/nvgpu/gp10b/hal_gp10b.c
View File

@@ -614,6 +614,8 @@ static const struct gpu_ops gp10b_ops = {
.halt_pipe = nvgpu_gr_falcon_halt_pipe,
.disable_ctxsw = nvgpu_gr_falcon_disable_ctxsw,
.enable_ctxsw = nvgpu_gr_falcon_enable_ctxsw,
.get_current_ctx = gm20b_gr_falcon_get_current_ctx,
.get_ctx_ptr = gm20b_gr_falcon_get_ctx_ptr,
},
},
.fb = {

2
drivers/gpu/nvgpu/gv100/hal_gv100.c
View File

@@ -758,6 +758,8 @@ static const struct gpu_ops gv100_ops = {
.halt_pipe = nvgpu_gr_falcon_halt_pipe,
.disable_ctxsw = nvgpu_gr_falcon_disable_ctxsw,
.enable_ctxsw = nvgpu_gr_falcon_enable_ctxsw,
.get_current_ctx = gm20b_gr_falcon_get_current_ctx,
.get_ctx_ptr = gm20b_gr_falcon_get_ctx_ptr,
},
},
.fb = {

2
drivers/gpu/nvgpu/gv11b/gr_gv11b.c
View File

@@ -1218,7 +1218,7 @@ int gr_gv11b_dump_gr_status_regs(struct gk20a *g,
gk20a_debug_output(o, "NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_IDLESTATE : 0x%x\n",
gk20a_readl(g, gr_gpc0_gpccs_ctxsw_idlestate_r()));
gk20a_debug_output(o, "NV_PGRAPH_PRI_FECS_CURRENT_CTX : 0x%x\n",
gk20a_readl(g, gr_fecs_current_ctx_r()));
g->ops.gr.falcon.get_current_ctx(g));
gk20a_debug_output(o, "NV_PGRAPH_PRI_FECS_NEW_CTX : 0x%x\n",
gk20a_readl(g, gr_fecs_new_ctx_r()));
gk20a_debug_output(o, "NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE : 0x%x\n",

2
drivers/gpu/nvgpu/gv11b/hal_gv11b.c
View File

@@ -717,6 +717,8 @@ static const struct gpu_ops gv11b_ops = {
.halt_pipe = nvgpu_gr_falcon_halt_pipe,
.disable_ctxsw = nvgpu_gr_falcon_disable_ctxsw,
.enable_ctxsw = nvgpu_gr_falcon_enable_ctxsw,
.get_current_ctx = gm20b_gr_falcon_get_current_ctx,
.get_ctx_ptr = gm20b_gr_falcon_get_ctx_ptr,
},
},
.fb = {

10
drivers/gpu/nvgpu/hal/gr/falcon/gr_falcon_gm20b.c
View File

@@ -798,3 +798,13 @@ int gm20b_gr_falcon_ctrl_ctxsw(struct gk20a *g, u32 fecs_method,
}
return gm20b_gr_falcon_submit_fecs_method_op(g, op, sleepduringwait);
}
u32 gm20b_gr_falcon_get_current_ctx(struct gk20a *g)
{
return nvgpu_readl(g, gr_fecs_current_ctx_r());
}
u32 gm20b_gr_falcon_get_ctx_ptr(u32 ctx)
{
return gr_fecs_current_ctx_ptr_v(ctx);
}

3
drivers/gpu/nvgpu/hal/gr/falcon/gr_falcon_gm20b.h
View File

@@ -66,4 +66,7 @@ int gm20b_gr_falcon_ctrl_ctxsw(struct gk20a *g, u32 fecs_method,
void gm20b_gr_falcon_set_current_ctx_invalid(struct gk20a *g);
u32 gm20b_gr_falcon_get_current_ctx(struct gk20a *g);
u32 gm20b_gr_falcon_get_ctx_ptr(u32 ctx);
#endif /* NVGPU_GR_FALCON_GM20B_H */

2
drivers/gpu/nvgpu/include/nvgpu/gk20a.h
View File

@@ -591,6 +591,8 @@ struct gpu_ops {
int (*halt_pipe)(struct gk20a *g);
int (*disable_ctxsw)(struct gk20a *g);
int (*enable_ctxsw)(struct gk20a *g);
u32 (*get_current_ctx)(struct gk20a *g);
u32 (*get_ctx_ptr)(u32 ctx);
} falcon;
#ifdef CONFIG_GK20A_CTXSW_TRACE

2
drivers/gpu/nvgpu/tu104/hal_tu104.c
View File

@@ -790,6 +790,8 @@ static const struct gpu_ops tu104_ops = {
.halt_pipe = nvgpu_gr_falcon_halt_pipe,
.disable_ctxsw = nvgpu_gr_falcon_disable_ctxsw,
.enable_ctxsw = nvgpu_gr_falcon_enable_ctxsw,
.get_current_ctx = gm20b_gr_falcon_get_current_ctx,
.get_ctx_ptr = gm20b_gr_falcon_get_ctx_ptr,
},
},
.fb = {