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gpu: nvgpu: Update GM20b clock initialization

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- Removed unnecessary static "initialized" variable (sw_ready flag is
  protecting from multiple initializations, anyway).
- Used max frequency at min voltage to set initial configuration of
  GPCPLL in both NA and non-NA mode. For backward compatibility made
  sure initial PLL output rate do not exceed 1/3 of VCO minimum.

Bug 1555318

Change-Id: If970c27442ea1109d4503a322998a6a26159c345
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/552370
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
This commit is contained in:
Alex Frid
2014-09-30 15:23:59 -07:00
committed by Dan Willemsen
parent d451db8204
commit 0f762c8510
1 changed files with 17 additions and 16 deletions
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33
drivers/gpu/nvgpu/gm20b/clk_gm20b.c
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@@ -1065,7 +1065,7 @@ struct clk *gm20b_clk_get(struct gk20a *g)
static int gm20b_init_clk_setup_sw(struct gk20a *g)
{
struct clk_gk20a *clk = &g->clk;
static int initialized;
unsigned long safe_rate;
struct clk *ref;
bool calibrated;
@@ -1103,30 +1103,28 @@ static int gm20b_init_clk_setup_sw(struct gk20a *g)
clk->gpc_pll.id = GK20A_GPC_PLL;
clk->gpc_pll.clk_in = clk_get_rate(ref) / KHZ;
safe_rate = tegra_dvfs_get_therm_safe_fmax(
clk_get_parent(clk->tegra_clk));
safe_rate = safe_rate * (100 - DVFS_SAFE_MARGIN) / 100;
dvfs_safe_max_freq = rate_gpu_to_gpc2clk(safe_rate);
clk->gpc_pll.PL = DIV_ROUND_UP(gpc_pll_params.min_vco,
dvfs_safe_max_freq);
/* Initial frequency: 1/3 VCO min (low enough to be safe at Vmin) */
if (!initialized) {
initialized = 1;
clk->gpc_pll.M = 1;
clk->gpc_pll.N = DIV_ROUND_UP(gpc_pll_params.min_vco,
clk->gpc_pll.clk_in);
clk->gpc_pll.PL = 3;
clk->gpc_pll.freq = clk->gpc_pll.clk_in * clk->gpc_pll.N;
clk->gpc_pll.freq /= pl_to_div(clk->gpc_pll.PL);
}
clk->gpc_pll.M = 1;
clk->gpc_pll.N = DIV_ROUND_UP(gpc_pll_params.min_vco,
clk->gpc_pll.clk_in);
clk->gpc_pll.PL = max(clk->gpc_pll.PL, 3U);
clk->gpc_pll.freq = clk->gpc_pll.clk_in * clk->gpc_pll.N;
clk->gpc_pll.freq /= pl_to_div(clk->gpc_pll.PL);
calibrated = !clk_config_calibration_params(g);
#ifdef CONFIG_TEGRA_USE_NA_GPCPLL
if (ALLOW_NON_CALIBRATED_NA_MODE || calibrated) {
/* NA mode is supported only at max update rate 38.4 MHz */
if (clk->gpc_pll.clk_in == gpc_pll_params.max_u) {
unsigned long safe_rate;
clk->gpc_pll.mode = GPC_PLL_MODE_DVFS;
gpc_pll_params.min_u = gpc_pll_params.max_u;
safe_rate = tegra_dvfs_get_therm_safe_fmax(
clk_get_parent(clk->tegra_clk));
safe_rate = safe_rate * (100 - DVFS_SAFE_MARGIN) / 100;
dvfs_safe_max_freq = rate_gpu_to_gpc2clk(safe_rate);
}
}
#endif
@@ -1136,6 +1134,9 @@ static int gm20b_init_clk_setup_sw(struct gk20a *g)
clk->sw_ready = true;
gk20a_dbg_fn("done");
pr_info("GM20b GPCPLL initial settings:%s M=%u, N=%u, P=%u\n",
clk->gpc_pll.mode == GPC_PLL_MODE_DVFS ? " NA mode," : "",
clk->gpc_pll.M, clk->gpc_pll.N, clk->gpc_pll.PL);
return 0;
}