gpu: nvgpu: PMU FBQ cmd/msg update

-Message header is added as part of FB message queue to have
 sequence number & checksum to perform sanity check on
 received message.
-Made required changes in structs to read message correctly
 from data member offset but skipped to handle sanity checks
 in code as NvGPU not needed for current supported messages .
-Added support to handle cmd/msg queue element changes.

JIRA NVGPU-3724

Change-Id: I85dccfab8902cbf71752582666931f482c3ec408
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2155165
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

drivers/gpu/nvgpu/common/engine_queues/engine_fb_queue.c

@@ -414,7 +414,8 @@ int nvgpu_engine_fb_queue_pop(struct nvgpu_engine_fb_queue *queue,
 	}
 
 	g = queue->g;
-	hdr = (struct pmu_hdr *) (void *) queue->fbq.work_buffer;
+	hdr = (struct pmu_hdr *) (void *) (queue->fbq.work_buffer +
+			sizeof(struct nv_falcon_fbq_msgq_hdr));
 
 	nvgpu_log_fn(g, " ");
 
@@ -470,7 +471,9 @@ int nvgpu_engine_fb_queue_pop(struct nvgpu_engine_fb_queue *queue,
 	}
 
 	nvgpu_memcpy((u8 *)data, (u8 *)queue->fbq.work_buffer +
-		queue->fbq.read_position, size);
+		queue->fbq.read_position +
+		sizeof(struct nv_falcon_fbq_msgq_hdr),
+		size);
 
 	/* update current position */
 	queue->fbq.read_position += size;

drivers/gpu/nvgpu/common/pmu/ipc/pmu_msg.c

@@ -330,6 +330,8 @@ static void pmu_read_init_msg_fb(struct gk20a *g, struct nvgpu_pmu *pmu,
 		nvgpu_pmu_get_ss_msg_fbq_element_offset(g, pmu,
 			pmu->super_surface, element_index);
 
+	fbq_msg_queue_ss_offset = nvgpu_safe_add_u32(fbq_msg_queue_ss_offset,
+			(u32)sizeof(struct nv_falcon_fbq_msgq_hdr));
 	nvgpu_mem_rd_n(g, nvgpu_pmu_super_surface_mem(g,
 		pmu, pmu->super_surface), fbq_msg_queue_ss_offset,
 		buffer, size);

drivers/gpu/nvgpu/include/nvgpu/flcnif_cmn.h

@@ -141,4 +141,11 @@ struct nv_falcon_fbq_hdr {
 	u16   heap_offset;
 };
 
+/* Header for a FB MSG Queue Entry */
+struct nv_falcon_fbq_msgq_hdr {
+	/* Queue level sequence number. */
+	u16   sequence_number;
+	/* Negative checksum of entire queue entry. */
+	u16   checksum;
+};
 #endif /* NVGPU_FLCNIF_CMN_H */

drivers/gpu/nvgpu/include/nvgpu/pmu/pmuif/nvgpu_cmdif.h

@@ -69,6 +69,10 @@
 /* Size of a single element in the MSG queue. */
 #define NV_PMU_FBQ_MSG_ELEMENT_SIZE		64U
 
+#define RM_PMU_FBQ_MSG_DATA_SIZE \
+	(NV_PMU_FBQ_MSG_ELEMENT_SIZE - \
+	sizeof(struct nv_falcon_fbq_msgq_hdr))
+
 /* Number of elements in each queue. */
 #define NV_PMU_FBQ_MSG_NUM_ELEMENTS		16U
 
@@ -78,13 +82,23 @@
 /* structure for a single PMU FB CMD queue entry */
 struct nv_pmu_fbq_cmd_q_element {
 	struct nv_falcon_fbq_hdr fbq_hdr;
-	u8 data[NV_PMU_FBQ_CMD_ELEMENT_SIZE -
-			sizeof(struct nv_falcon_fbq_hdr)];
+
+	struct {
+		struct pmu_hdr hdr;
+		u8 bytes[NV_PMU_FBQ_CMD_ELEMENT_SIZE -
+			sizeof(struct nv_falcon_fbq_hdr) -
+			sizeof(struct pmu_hdr)];
+	} data;
 };
 
 /* structure for a single PMU FB MSG queue entry */
 struct nv_pmu_fbq_msg_q_element {
-	u8 data[NV_PMU_FBQ_MSG_ELEMENT_SIZE];
+	struct nv_falcon_fbq_msgq_hdr fbq_msg_hdr;
+	struct {
+		struct pmu_hdr hdr;
+		u8 bytes[RM_PMU_FBQ_MSG_DATA_SIZE -
+				sizeof(struct pmu_hdr)];
+	} data;
 };
 
 /* structure for a single FB CMD queue */