gpu: nvgpu: gr: reduce code complexity in ctxsw_preemption_mode

nvgpu_gr_obj_ctx_set_ctxsw_preemption_mode function code
complexity reduced from 13 to 8 by using following helper
functions:
1. nvgpu_gr_obj_ctx_set_graphics_preemption_mode:
					code complexity 4
2. nvgpu_gr_obj_ctx_set_compute_preemption_mode:
					code complexity 4

JIRA NVGPU-3581

Change-Id: I70d79d98e7beb13fcee578ea4ac6112096b8933d
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2178751
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Seshendra Gadagottu
2019-08-19 15:59:11 -07:00
committed by mobile promotions
parent 7eab528d34
commit 107888ff23

View File

@@ -111,38 +111,13 @@ static int nvgpu_gr_obj_ctx_init_ctxsw_preemption_mode(struct gk20a *g,
return 0;
}
int nvgpu_gr_obj_ctx_set_ctxsw_preemption_mode(struct gk20a *g,
static int nvgpu_gr_obj_ctx_set_graphics_preemption_mode(struct gk20a *g,
struct nvgpu_gr_config *config, struct nvgpu_gr_ctx_desc *gr_ctx_desc,
struct nvgpu_gr_ctx *gr_ctx, struct vm_gk20a *vm, u32 class_num,
u32 graphics_preempt_mode, u32 compute_preempt_mode)
struct nvgpu_gr_ctx *gr_ctx, struct vm_gk20a *vm,
u32 graphics_preempt_mode)
{
int err = 0;
#ifdef CONFIG_NVGPU_GRAPHICS
if (!nvgpu_is_enabled(g, NVGPU_SUPPORT_PREEMPTION_GFXP)) {
return 0;
}
if (g->ops.gpu_class.is_valid_gfx(class_num) &&
nvgpu_gr_ctx_desc_force_preemption_gfxp(gr_ctx_desc)) {
graphics_preempt_mode = NVGPU_PREEMPTION_MODE_GRAPHICS_GFXP;
}
#endif
#ifdef CONFIG_NVGPU_CILP
if (g->ops.gpu_class.is_valid_compute(class_num) &&
nvgpu_gr_ctx_desc_force_preemption_cilp(gr_ctx_desc)) {
compute_preempt_mode = NVGPU_PREEMPTION_MODE_COMPUTE_CILP;
}
#endif
/* check for invalid combinations */
if (nvgpu_gr_ctx_check_valid_preemption_mode(gr_ctx,
graphics_preempt_mode, compute_preempt_mode) == false) {
err = -EINVAL;
goto fail;
}
/* set preemption modes */
switch (graphics_preempt_mode) {
#ifdef CONFIG_NVGPU_GRAPHICS
@@ -198,6 +173,16 @@ int nvgpu_gr_obj_ctx_set_ctxsw_preemption_mode(struct gk20a *g,
break;
}
#ifdef CONFIG_NVGPU_GRAPHICS
fail:
#endif
return err;
}
static int nvgpu_gr_obj_ctx_set_compute_preemption_mode(struct gk20a *g,
struct nvgpu_gr_ctx *gr_ctx, u32 class_num, u32 compute_preempt_mode)
{
if (g->ops.gpu_class.is_valid_compute(class_num) ||
g->ops.gpu_class.is_valid_gfx(class_num)) {
switch (compute_preempt_mode) {
@@ -217,6 +202,52 @@ int nvgpu_gr_obj_ctx_set_ctxsw_preemption_mode(struct gk20a *g,
}
return 0;
}
int nvgpu_gr_obj_ctx_set_ctxsw_preemption_mode(struct gk20a *g,
struct nvgpu_gr_config *config, struct nvgpu_gr_ctx_desc *gr_ctx_desc,
struct nvgpu_gr_ctx *gr_ctx, struct vm_gk20a *vm, u32 class_num,
u32 graphics_preempt_mode, u32 compute_preempt_mode)
{
int err = 0;
#ifdef CONFIG_NVGPU_GRAPHICS
if (!nvgpu_is_enabled(g, NVGPU_SUPPORT_PREEMPTION_GFXP)) {
return 0;
}
if (g->ops.gpu_class.is_valid_gfx(class_num) &&
nvgpu_gr_ctx_desc_force_preemption_gfxp(gr_ctx_desc)) {
graphics_preempt_mode = NVGPU_PREEMPTION_MODE_GRAPHICS_GFXP;
}
#endif
#ifdef CONFIG_NVGPU_CILP
if (g->ops.gpu_class.is_valid_compute(class_num) &&
nvgpu_gr_ctx_desc_force_preemption_cilp(gr_ctx_desc)) {
compute_preempt_mode = NVGPU_PREEMPTION_MODE_COMPUTE_CILP;
}
#endif
/* check for invalid combinations */
if (nvgpu_gr_ctx_check_valid_preemption_mode(gr_ctx,
graphics_preempt_mode, compute_preempt_mode) == false) {
err = -EINVAL;
goto fail;
}
err = nvgpu_gr_obj_ctx_set_graphics_preemption_mode(g, config,
gr_ctx_desc, gr_ctx, vm, graphics_preempt_mode);
if (err != 0) {
goto fail;
}
err = nvgpu_gr_obj_ctx_set_compute_preemption_mode(g, gr_ctx,
class_num, compute_preempt_mode);
fail:
return err;