gpu: nvgpu: rename runlist HALs for mem access

Renamed
- runlist_gk20a.c -> runlist_ram_gk20a.c
- runlist_gk20a.h -> runlist_ram_gk20a.h
- runlist_gv11b.c -> runlist_ram_gv11b.c
- runlist_gv11b.h -> runlist_ram_gv11b.h
- runlist_tu104.c -> runlist_ram_tu104.c
- runlist_tu104.h -> runlist_ram_tu104.h

Updated makefiles and include files.

Jira NVGPU-3198

Change-Id: Id65654990470bbf0bc79655d2f5efcb226dae220
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2107604
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

drivers/gpu/nvgpu/Makefile

@@ -283,9 +283,9 @@ nvgpu-y += \
 	hal/fifo/ramin_gp10b.o \
 	hal/fifo/ramin_gv11b.o \
 	hal/fifo/ramin_tu104.o \
-	hal/fifo/runlist_gk20a.o \
-	hal/fifo/runlist_gv11b.o \
-	hal/fifo/runlist_tu104.o \
+	hal/fifo/runlist_ram_gk20a.o \
+	hal/fifo/runlist_ram_gv11b.o \
+	hal/fifo/runlist_ram_tu104.o \
 	hal/fifo/runlist_fifo_gk20a.o \
 	hal/fifo/runlist_fifo_gv11b.o \
 	hal/fifo/runlist_fifo_gv100.o \

drivers/gpu/nvgpu/Makefile.sources

@@ -385,9 +385,9 @@ srcs += common/sim/sim.c \
 	hal/fifo/ramin_gp10b.c \
 	hal/fifo/ramin_gv11b.c \
 	hal/fifo/ramin_tu104.c \
-	hal/fifo/runlist_gk20a.c \
-	hal/fifo/runlist_gv11b.c \
-	hal/fifo/runlist_tu104.c \
+	hal/fifo/runlist_ram_gk20a.c \
+	hal/fifo/runlist_ram_gv11b.c \
+	hal/fifo/runlist_ram_tu104.c \
 	hal/fifo/runlist_fifo_gk20a.c \
 	hal/fifo/runlist_fifo_gv11b.c \
 	hal/fifo/runlist_fifo_gv100.c \

drivers/gpu/nvgpu/common/vgpu/gp10b/vgpu_hal_gp10b.c

@@ -43,7 +43,7 @@
 #include "hal/fifo/ramin_gk20a.h"
 #include "hal/fifo/ramin_gm20b.h"
 #include "hal/fifo/ramin_gp10b.h"
-#include "hal/fifo/runlist_gk20a.h"
+#include "hal/fifo/runlist_ram_gk20a.h"
 #include "hal/fifo/runlist_fifo_gk20a.h"
 #include "hal/fifo/userd_gk20a.h"
 #include "hal/fifo/mmu_fault_gm20b.h"

drivers/gpu/nvgpu/common/vgpu/gv11b/vgpu_hal_gv11b.c

@@ -36,7 +36,7 @@
 #include "hal/fifo/ramin_gm20b.h"
 #include "hal/fifo/ramin_gp10b.h"
 #include "hal/fifo/ramin_gv11b.h"
-#include "hal/fifo/runlist_gv11b.h"
+#include "hal/fifo/runlist_ram_gv11b.h"
 #include "hal/fifo/runlist_fifo_gv11b.h"
 #include "hal/fifo/tsg_gv11b.h"
 #include "hal/fifo/userd_gk20a.h"

drivers/gpu/nvgpu/hal/fifo/runlist_ram_gk20a.c

@@ -28,7 +28,7 @@
 #include <nvgpu/engines.h>
 #include <nvgpu/gr/gr_falcon.h>
 
-#include "runlist_gk20a.h"
+#include "runlist_ram_gk20a.h"
 
 #include <nvgpu/hw/gk20a/hw_ram_gk20a.h>
 

drivers/gpu/nvgpu/hal/fifo/runlist_ram_gk20a.h

@@ -20,8 +20,8 @@
  * DEALINGS IN THE SOFTWARE.
  */
 
-#ifndef NVGPU_RUNLIST_GK20A_H
-#define NVGPU_RUNLIST_GK20A_H
+#ifndef NVGPU_RUNLIST_RAM_GK20A_H
+#define NVGPU_RUNLIST_RAM_GK20A_H
 
 #include <nvgpu/types.h>
 
@@ -34,4 +34,4 @@ void gk20a_runlist_get_tsg_entry(struct tsg_gk20a *tsg,
 		u32 *runlist, u32 timeslice);
 void gk20a_runlist_get_ch_entry(struct channel_gk20a *ch, u32 *runlist);
 
-#endif /* NVGPU_RUNLIST_GK20A_H */
+#endif /* NVGPU_RUNLIST_RAM_GK20A_H */

drivers/gpu/nvgpu/hal/fifo/runlist_ram_gv11b.c

@@ -24,7 +24,7 @@
 #include <nvgpu/runlist.h>
 #include <nvgpu/gk20a.h>
 
-#include "runlist_gv11b.h"
+#include "runlist_ram_gv11b.h"
 
 #include <nvgpu/hw/gv11b/hw_ram_gv11b.h>
 
@@ -76,18 +76,17 @@ void gv11b_runlist_get_ch_entry(struct channel_gk20a *ch, u32 *runlist)
 
 	/* Time being use 0 pbdma sequencer */
 	runlist_entry = ram_rl_entry_type_channel_v() |
-			ram_rl_entry_chan_runqueue_selector_f(
-						ch->runqueue_sel) |
-			ram_rl_entry_chan_userd_target_f(
-				nvgpu_aperture_mask(g, ch->userd_mem,
-					ram_rl_entry_chan_userd_target_sys_mem_ncoh_v(),
-					ram_rl_entry_chan_userd_target_sys_mem_coh_v(),
-					ram_rl_entry_chan_userd_target_vid_mem_v())) |
-			ram_rl_entry_chan_inst_target_f(
-				nvgpu_aperture_mask(g, &ch->inst_block,
-					ram_rl_entry_chan_inst_target_sys_mem_ncoh_v(),
-					ram_rl_entry_chan_inst_target_sys_mem_coh_v(),
-					ram_rl_entry_chan_inst_target_vid_mem_v()));
+		ram_rl_entry_chan_runqueue_selector_f(ch->runqueue_sel) |
+		ram_rl_entry_chan_userd_target_f(
+			nvgpu_aperture_mask(g, ch->userd_mem,
+				ram_rl_entry_chan_userd_target_sys_mem_ncoh_v(),
+				ram_rl_entry_chan_userd_target_sys_mem_coh_v(),
+				ram_rl_entry_chan_userd_target_vid_mem_v())) |
+		ram_rl_entry_chan_inst_target_f(
+			nvgpu_aperture_mask(g, &ch->inst_block,
+				ram_rl_entry_chan_inst_target_sys_mem_ncoh_v(),
+				ram_rl_entry_chan_inst_target_sys_mem_coh_v(),
+				ram_rl_entry_chan_inst_target_vid_mem_v()));
 
 	addr_lo = u64_lo32(ch->userd_iova) >>
 			ram_rl_entry_chan_userd_ptr_align_shift_v();

drivers/gpu/nvgpu/hal/fifo/runlist_ram_gv11b.h

@@ -20,8 +20,8 @@
  * DEALINGS IN THE SOFTWARE.
  */
 
-#ifndef NVGPU_RUNLIST_GV11B_H
-#define NVGPU_RUNLIST_GV11B_H
+#ifndef NVGPU_RUNLIST_RAM_GV11B_H
+#define NVGPU_RUNLIST_RAM_GV11B_H
 
 #include <nvgpu/types.h>
 
@@ -33,4 +33,4 @@ void gv11b_runlist_get_tsg_entry(struct tsg_gk20a *tsg,
 		u32 *runlist, u32 timeslice);
 void gv11b_runlist_get_ch_entry(struct channel_gk20a *ch, u32 *runlist);
 
-#endif /* NVGPU_RUNLIST_GV11B_H */
+#endif /* NVGPU_RUNLIST_RAM_GV11B_H */

drivers/gpu/nvgpu/hal/fifo/runlist_ram_tu104.c

@@ -20,7 +20,7 @@
  * DEALINGS IN THE SOFTWARE.
  */
 
-#include "runlist_tu104.h"
+#include "runlist_ram_tu104.h"
 
 #include <nvgpu/hw/tu104/hw_ram_tu104.h>
 

drivers/gpu/nvgpu/hal/fifo/runlist_ram_tu104.h

@@ -20,8 +20,8 @@
  * DEALINGS IN THE SOFTWARE.
  */
 
-#ifndef NVGPU_RUNLIST_TU104_H
-#define NVGPU_RUNLIST_TU104_H
+#ifndef NVGPU_RUNLIST_RAM_TU104_H
+#define NVGPU_RUNLIST_RAM_TU104_H
 
 #include <nvgpu/types.h>
 
@@ -29,4 +29,4 @@ struct gk20a;
 
 u32 tu104_runlist_entry_size(struct gk20a *g);
 
-#endif /* NVGPU_RUNLIST_TU104_H */
+#endif /* NVGPU_RUNLIST_RAM_TU104_H */

drivers/gpu/nvgpu/hal/init/hal_gm20b.c

@@ -67,7 +67,7 @@
 #include "hal/fifo/ramfc_gk20a.h"
 #include "hal/fifo/ramin_gk20a.h"
 #include "hal/fifo/ramin_gm20b.h"
-#include "hal/fifo/runlist_gk20a.h"
+#include "hal/fifo/runlist_ram_gk20a.h"
 #include "hal/fifo/runlist_fifo_gk20a.h"
 #include "hal/fifo/tsg_gk20a.h"
 #include "hal/fifo/userd_gk20a.h"

drivers/gpu/nvgpu/hal/init/hal_gp10b.c

@@ -79,7 +79,7 @@
 #include "hal/fifo/ramin_gk20a.h"
 #include "hal/fifo/ramin_gm20b.h"
 #include "hal/fifo/ramin_gp10b.h"
-#include "hal/fifo/runlist_gk20a.h"
+#include "hal/fifo/runlist_ram_gk20a.h"
 #include "hal/fifo/runlist_fifo_gk20a.h"
 #include "hal/fifo/tsg_gk20a.h"
 #include "hal/fifo/userd_gk20a.h"

drivers/gpu/nvgpu/hal/init/hal_gv100.c

@@ -77,8 +77,8 @@
 #include "hal/fifo/ramin_gm20b.h"
 #include "hal/fifo/ramin_gp10b.h"
 #include "hal/fifo/ramin_gv11b.h"
-#include "hal/fifo/runlist_gk20a.h"
-#include "hal/fifo/runlist_gv11b.h"
+#include "hal/fifo/runlist_ram_gk20a.h"
+#include "hal/fifo/runlist_ram_gv11b.h"
 #include "hal/fifo/runlist_fifo_gk20a.h"
 #include "hal/fifo/runlist_fifo_gv11b.h"
 #include "hal/fifo/runlist_fifo_gv100.h"

drivers/gpu/nvgpu/hal/init/hal_gv11b.c

@@ -80,8 +80,8 @@
 #include "hal/fifo/ramin_gm20b.h"
 #include "hal/fifo/ramin_gp10b.h"
 #include "hal/fifo/ramin_gv11b.h"
-#include "hal/fifo/runlist_gk20a.h"
-#include "hal/fifo/runlist_gv11b.h"
+#include "hal/fifo/runlist_ram_gk20a.h"
+#include "hal/fifo/runlist_ram_gv11b.h"
 #include "hal/fifo/runlist_fifo_gk20a.h"
 #include "hal/fifo/runlist_fifo_gv11b.h"
 #include "hal/fifo/tsg_gv11b.h"

drivers/gpu/nvgpu/hal/init/hal_tu104.c

@@ -82,9 +82,9 @@
 #include "hal/fifo/ramin_gp10b.h"
 #include "hal/fifo/ramin_gv11b.h"
 #include "hal/fifo/ramin_tu104.h"
-#include "hal/fifo/runlist_gk20a.h"
-#include "hal/fifo/runlist_gv11b.h"
-#include "hal/fifo/runlist_tu104.h"
+#include "hal/fifo/runlist_ram_gk20a.h"
+#include "hal/fifo/runlist_ram_gv11b.h"
+#include "hal/fifo/runlist_ram_tu104.h"
 #include "hal/fifo/runlist_fifo_gk20a.h"
 #include "hal/fifo/runlist_fifo_gv11b.h"
 #include "hal/fifo/runlist_fifo_tu104.h"

userspace/units/fifo/runlist/nvgpu-runlist.c

@@ -29,7 +29,7 @@
 #include <nvgpu/runlist.h>
 #include <nvgpu/gk20a.h>
 
-#include "hal/fifo/runlist_gk20a.h"
+#include "hal/fifo/runlist_ram_gk20a.h"
 #include "hal/fifo/tsg_gk20a.h"
 
 static void setup_fifo(struct gk20a *g, unsigned long *tsg_map,