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gpu: nvgpu: rearrange zbc hal functions

Browse Source 
As part of creating zbc as gr subunit, zbc hal functions in gr
are moved under struct zbc.

Removed unused function - _gk20a_gr_zbc_set_table
Removed unused hal function -  add_zbc

JIRA NVGPU-1882

Change-Id: I7560135210c45abb734d4041b3f7330a988b6978
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2017812
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Vinod G
2019-02-12 17:03:51 -08:00
committed by mobile promotions
parent 60402c78b3
commit 10d6603f39
14 changed files with 167 additions and 164 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/gpu/nvgpu/common/pmu/pmu.c
View File

@@ -576,7 +576,7 @@ static void pmu_setup_hw_enable_elpg(struct gk20a *g)
if (nvgpu_is_enabled(g, NVGPU_PMU_ZBC_SAVE)) {
/* Save zbc table after PMU is initialized. */
pmu->zbc_ready = true;
g->ops.gr.pmu_save_zbc(g, 0xf);
g->ops.gr.zbc.pmu_save(g, 0xf);
}
if (g->elpg_enabled) {

65
drivers/gpu/nvgpu/gk20a/gr_gk20a.c
View File

@@ -2587,7 +2587,7 @@ void gr_gk20a_pmu_save_zbc(struct gk20a *g, u32 entries)
}
/* update zbc */
g->ops.gr.pmu_save_zbc(g, entries);
g->ops.gr.zbc.pmu_save(g, entries);
clean_up:
ret = gk20a_fifo_enable_engine_activity(g, gr_info);
@@ -2641,7 +2641,7 @@ int gr_gk20a_add_zbc(struct gk20a *g, struct gr_gk20a *gr,
&gr->zbc_col_tbl[gr->max_used_color_index];
WARN_ON(c_tbl->ref_cnt != 0U);
ret = g->ops.gr.add_zbc_color(g, gr,
ret = g->ops.gr.zbc.add_color(g, gr,
zbc_val, gr->max_used_color_index);
if (ret == 0) {
@@ -2672,7 +2672,7 @@ int gr_gk20a_add_zbc(struct gk20a *g, struct gr_gk20a *gr,
&gr->zbc_dep_tbl[gr->max_used_depth_index];
WARN_ON(d_tbl->ref_cnt != 0U);
ret = g->ops.gr.add_zbc_depth(g, gr,
ret = g->ops.gr.zbc.add_depth(g, gr,
zbc_val, gr->max_used_depth_index);
if (ret == 0) {
@@ -2681,8 +2681,9 @@ int gr_gk20a_add_zbc(struct gk20a *g, struct gr_gk20a *gr,
}
break;
case T19X_ZBC:
if (g->ops.gr.add_zbc_type_s != NULL) {
added = g->ops.gr.add_zbc_type_s(g, gr, zbc_val, &ret);
if (g->ops.gr.zbc.add_type_stencil != NULL) {
added = g->ops.gr.zbc.add_type_stencil(g, gr,
zbc_val, &ret);
} else {
nvgpu_err(g,
"invalid zbc table type %d", zbc_val->type);
@@ -2701,7 +2702,7 @@ int gr_gk20a_add_zbc(struct gk20a *g, struct gr_gk20a *gr,
/* update zbc for elpg only when new entry is added */
entries = max(gr->max_used_color_index,
gr->max_used_depth_index);
g->ops.gr.pmu_save_zbc(g, entries);
g->ops.gr.zbc.pmu_save(g, entries);
}
err_mutex:
@@ -2752,8 +2753,8 @@ int gr_gk20a_query_zbc(struct gk20a *g, struct gr_gk20a *gr,
query_params->ref_cnt = gr->zbc_dep_tbl[index].ref_cnt;
break;
case T19X_ZBC:
if (g->ops.gr.zbc_s_query_table != NULL) {
return g->ops.gr.zbc_s_query_table(g, gr,
if (g->ops.gr.zbc.stencil_query_table != NULL) {
return g->ops.gr.zbc.stencil_query_table(g, gr,
query_params);
} else {
nvgpu_err(g,
@@ -2786,7 +2787,7 @@ static int gr_gk20a_load_zbc_table(struct gk20a *g, struct gr_gk20a *gr)
(u8 *)c_tbl->color_l2, sizeof(zbc_val.color_l2));
zbc_val.format = c_tbl->format;
ret = g->ops.gr.add_zbc_color(g, gr, &zbc_val, i);
ret = g->ops.gr.zbc.add_color(g, gr, &zbc_val, i);
if (ret != 0) {
return ret;
@@ -2800,14 +2801,14 @@ static int gr_gk20a_load_zbc_table(struct gk20a *g, struct gr_gk20a *gr)
zbc_val.depth = d_tbl->depth;
zbc_val.format = d_tbl->format;
ret = g->ops.gr.add_zbc_depth(g, gr, &zbc_val, i);
ret = g->ops.gr.zbc.add_depth(g, gr, &zbc_val, i);
if (ret != 0) {
return ret;
}
}
if (g->ops.gr.load_zbc_s_tbl != NULL) {
ret = g->ops.gr.load_zbc_s_tbl(g, gr);
if (g->ops.gr.zbc.load_stencil_tbl != NULL) {
ret = g->ops.gr.zbc.load_stencil_tbl(g, gr);
if (ret != 0) {
return ret;
}
@@ -2887,8 +2888,8 @@ int gr_gk20a_load_zbc_default_table(struct gk20a *g, struct gr_gk20a *gr)
gr->max_default_depth_index = 2;
if (g->ops.gr.load_zbc_s_default_tbl != NULL) {
err = g->ops.gr.load_zbc_s_default_tbl(g, gr);
if (g->ops.gr.zbc.load_stencil_default_tbl != NULL) {
err = g->ops.gr.zbc.load_stencil_default_tbl(g, gr);
if (err != 0) {
return err;
}
@@ -2904,42 +2905,6 @@ depth_fail:
return err;
}
int _gk20a_gr_zbc_set_table(struct gk20a *g, struct gr_gk20a *gr,
struct zbc_entry *zbc_val)
{
struct fifo_gk20a *f = &g->fifo;
struct fifo_engine_info_gk20a *gr_info = NULL;
int ret;
u32 engine_id;
engine_id = nvgpu_engine_get_gr_eng_id(g);
gr_info = (f->engine_info + engine_id);
ret = gk20a_fifo_disable_engine_activity(g, gr_info, true);
if (ret != 0) {
nvgpu_err(g,
"failed to disable gr engine activity");
return ret;
}
ret = g->ops.gr.wait_empty(g);
if (ret != 0) {
nvgpu_err(g,
"failed to idle graphics");
goto clean_up;
}
ret = gr_gk20a_add_zbc(g, gr, zbc_val);
clean_up:
if (gk20a_fifo_enable_engine_activity(g, gr_info) != 0) {
nvgpu_err(g,
"failed to enable gr engine activity");
}
return ret;
}
int gk20a_gr_zbc_set_table(struct gk20a *g, struct gr_gk20a *gr,
struct zbc_entry *zbc_val)
{

2
drivers/gpu/nvgpu/gk20a/gr_gk20a.h
View File

@@ -548,8 +548,6 @@ int gr_gk20a_add_zbc_color(struct gk20a *g, struct gr_gk20a *gr,
struct zbc_entry *color_val, u32 index);
int gr_gk20a_add_zbc_depth(struct gk20a *g, struct gr_gk20a *gr,
struct zbc_entry *depth_val, u32 index);
int _gk20a_gr_zbc_set_table(struct gk20a *g, struct gr_gk20a *gr,
struct zbc_entry *zbc_val);
void gr_gk20a_pmu_save_zbc(struct gk20a *g, u32 entries);
int gr_gk20a_wait_idle(struct gk20a *g);
int gr_gk20a_handle_sm_exception(struct gk20a *g, u32 gpc, u32 tpc, u32 sm,

20
drivers/gpu/nvgpu/gm20b/hal_gm20b.c
View File

@@ -251,12 +251,6 @@ static const struct gpu_ops gm20b_ops = {
.is_tpc_addr = gr_gm20b_is_tpc_addr,
.get_tpc_num = gr_gm20b_get_tpc_num,
.detect_sm_arch = gr_gm20b_detect_sm_arch,
.add_zbc_color = gr_gk20a_add_zbc_color,
.add_zbc_depth = gr_gk20a_add_zbc_depth,
.zbc_set_table = gk20a_gr_zbc_set_table,
.zbc_query_table = gr_gk20a_query_zbc,
.pmu_save_zbc = gk20a_pmu_save_zbc,
.add_zbc = gr_gk20a_add_zbc,
.pagepool_default_size = gr_gm20b_pagepool_default_size,
.init_ctx_state = gr_gk20a_init_ctx_state,
.alloc_gr_ctx = gr_gk20a_alloc_gr_ctx,
@@ -414,6 +408,20 @@ static const struct gpu_ops gm20b_ops = {
.get_pes_tpc_mask = gm20b_gr_config_get_pes_tpc_mask,
.get_pd_dist_skip_table_size =
gm20b_gr_config_get_pd_dist_skip_table_size,
},
.zbc = {
.add_color = gr_gk20a_add_zbc_color,
.add_depth = gr_gk20a_add_zbc_depth,
.set_table = gk20a_gr_zbc_set_table,
.query_table = gr_gk20a_query_zbc,
.pmu_save = gk20a_pmu_save_zbc,
.stencil_query_table = NULL,
.load_stencil_default_tbl = NULL,
.add_type_stencil = NULL,
.load_stencil_tbl = NULL,
.add_stencil = NULL,
.get_gpcs_swdx_dss_zbc_c_format_reg = NULL,
.get_gpcs_swdx_dss_zbc_z_format_reg = NULL,
}
},
.fb = {

4
drivers/gpu/nvgpu/gp10b/gr_gp10b.c
View File

@@ -532,7 +532,7 @@ int gr_gp10b_add_zbc_color(struct gk20a *g, struct gr_gk20a *gr,
u32 i;
u32 zbc_c;
u32 zbc_c_format_reg =
g->ops.gr.get_gpcs_swdx_dss_zbc_c_format_reg(g);
g->ops.gr.zbc.get_gpcs_swdx_dss_zbc_c_format_reg(g);
/* update l2 table */
g->ops.ltc.set_zbc_color_entry(g, color_val, index);
@@ -571,7 +571,7 @@ int gr_gp10b_add_zbc_depth(struct gk20a *g, struct gr_gk20a *gr,
{
u32 zbc_z;
u32 zbc_z_format_reg =
g->ops.gr.get_gpcs_swdx_dss_zbc_z_format_reg(g);
g->ops.gr.zbc.get_gpcs_swdx_dss_zbc_z_format_reg(g);
/* update l2 table */
g->ops.ltc.set_zbc_depth_entry(g, depth_val, index);

26
drivers/gpu/nvgpu/gp10b/hal_gp10b.c
View File

@@ -272,16 +272,6 @@ static const struct gpu_ops gp10b_ops = {
.is_tpc_addr = gr_gm20b_is_tpc_addr,
.get_tpc_num = gr_gm20b_get_tpc_num,
.detect_sm_arch = gr_gm20b_detect_sm_arch,
.add_zbc_color = gr_gp10b_add_zbc_color,
.add_zbc_depth = gr_gp10b_add_zbc_depth,
.get_gpcs_swdx_dss_zbc_c_format_reg =
gr_gp10b_get_gpcs_swdx_dss_zbc_c_format_reg,
.get_gpcs_swdx_dss_zbc_z_format_reg =
gr_gp10b_get_gpcs_swdx_dss_zbc_z_format_reg,
.zbc_set_table = gk20a_gr_zbc_set_table,
.zbc_query_table = gr_gk20a_query_zbc,
.pmu_save_zbc = gk20a_pmu_save_zbc,
.add_zbc = gr_gk20a_add_zbc,
.pagepool_default_size = gr_gp10b_pagepool_default_size,
.init_ctx_state = gr_gp10b_init_ctx_state,
.alloc_gr_ctx = gr_gk20a_alloc_gr_ctx,
@@ -462,6 +452,22 @@ static const struct gpu_ops gp10b_ops = {
.get_pes_tpc_mask = gm20b_gr_config_get_pes_tpc_mask,
.get_pd_dist_skip_table_size =
gm20b_gr_config_get_pd_dist_skip_table_size,
},
.zbc = {
.add_color = gr_gp10b_add_zbc_color,
.add_depth = gr_gp10b_add_zbc_depth,
.set_table = gk20a_gr_zbc_set_table,
.query_table = gr_gk20a_query_zbc,
.pmu_save = gk20a_pmu_save_zbc,
.stencil_query_table = NULL,
.load_stencil_default_tbl = NULL,
.add_type_stencil = NULL,
.load_stencil_tbl = NULL,
.add_stencil = NULL,
.get_gpcs_swdx_dss_zbc_c_format_reg =
gr_gp10b_get_gpcs_swdx_dss_zbc_c_format_reg,
.get_gpcs_swdx_dss_zbc_z_format_reg =
gr_gp10b_get_gpcs_swdx_dss_zbc_z_format_reg,
}
},
.fb = {

32
drivers/gpu/nvgpu/gv100/hal_gv100.c
View File

@@ -373,16 +373,6 @@ static const struct gpu_ops gv100_ops = {
.is_tpc_addr = gr_gm20b_is_tpc_addr,
.get_tpc_num = gr_gm20b_get_tpc_num,
.detect_sm_arch = gr_gv11b_detect_sm_arch,
.add_zbc_color = gr_gp10b_add_zbc_color,
.add_zbc_depth = gr_gp10b_add_zbc_depth,
.get_gpcs_swdx_dss_zbc_c_format_reg =
gr_gv11b_get_gpcs_swdx_dss_zbc_c_format_reg,
.get_gpcs_swdx_dss_zbc_z_format_reg =
gr_gv11b_get_gpcs_swdx_dss_zbc_z_format_reg,
.zbc_set_table = gk20a_gr_zbc_set_table,
.zbc_query_table = gr_gk20a_query_zbc,
.pmu_save_zbc = gk20a_pmu_save_zbc,
.add_zbc = gr_gk20a_add_zbc,
.pagepool_default_size = gr_gv11b_pagepool_default_size,
.init_ctx_state = gr_gp10b_init_ctx_state,
.alloc_gr_ctx = gr_gk20a_alloc_gr_ctx,
@@ -461,19 +451,14 @@ static const struct gpu_ops gv100_ops = {
.is_etpc_addr = gv11b_gr_pri_is_etpc_addr,
.egpc_etpc_priv_addr_table = gv11b_gr_egpc_etpc_priv_addr_table,
.handle_tpc_mpc_exception = gr_gv11b_handle_tpc_mpc_exception,
.zbc_s_query_table = gr_gv11b_zbc_s_query_table,
.load_zbc_s_default_tbl = gr_gv11b_load_stencil_default_tbl,
.handle_gpc_gpcmmu_exception =
gr_gv11b_handle_gpc_gpcmmu_exception,
.add_zbc_type_s = gr_gv11b_add_zbc_type_s,
.get_egpc_base = gv11b_gr_get_egpc_base,
.get_egpc_etpc_num = gv11b_gr_get_egpc_etpc_num,
.handle_gpc_gpccs_exception =
gr_gv11b_handle_gpc_gpccs_exception,
.load_zbc_s_tbl = gr_gv11b_load_stencil_tbl,
.access_smpc_reg = gv11b_gr_access_smpc_reg,
.is_egpc_addr = gv11b_gr_pri_is_egpc_addr,
.add_zbc_s = gr_gv11b_add_zbc_stencil,
.handle_gcc_exception = gr_gv11b_handle_gcc_exception,
.init_sw_veid_bundle = gr_gv11b_init_sw_veid_bundle,
.decode_egpc_addr = gv11b_gr_decode_egpc_addr,
@@ -593,6 +578,23 @@ static const struct gpu_ops gv100_ops = {
.get_pes_tpc_mask = gm20b_gr_config_get_pes_tpc_mask,
.get_pd_dist_skip_table_size =
gm20b_gr_config_get_pd_dist_skip_table_size,
},
.zbc = {
.add_color = gr_gp10b_add_zbc_color,
.add_depth = gr_gp10b_add_zbc_depth,
.set_table = gk20a_gr_zbc_set_table,
.query_table = gr_gk20a_query_zbc,
.pmu_save = gk20a_pmu_save_zbc,
.stencil_query_table = gr_gv11b_zbc_s_query_table,
.load_stencil_default_tbl =
gr_gv11b_load_stencil_default_tbl,
.add_type_stencil = gr_gv11b_add_zbc_type_s,
.load_stencil_tbl = gr_gv11b_load_stencil_tbl,
.add_stencil = gr_gv11b_add_zbc_stencil,
.get_gpcs_swdx_dss_zbc_c_format_reg =
gr_gv11b_get_gpcs_swdx_dss_zbc_c_format_reg,
.get_gpcs_swdx_dss_zbc_z_format_reg =
gr_gv11b_get_gpcs_swdx_dss_zbc_z_format_reg,
}
},
.fb = {

14
drivers/gpu/nvgpu/gv11b/gr_gv11b.c
View File

@@ -1188,7 +1188,7 @@ bool gr_gv11b_add_zbc_type_s(struct gk20a *g, struct gr_gk20a *gr,
s_tbl = &gr->zbc_s_tbl[gr->max_used_s_index];
WARN_ON(s_tbl->ref_cnt != 0U);
*ret_val = g->ops.gr.add_zbc_s(g, gr,
*ret_val = g->ops.gr.zbc.add_stencil(g, gr,
zbc_val, gr->max_used_s_index);
if ((*ret_val) == 0) {
@@ -1204,19 +1204,21 @@ int gr_gv11b_add_zbc_stencil(struct gk20a *g, struct gr_gk20a *gr,
u32 zbc_s;
/* update l2 table */
g->ops.ltc.set_zbc_s_entry(g, stencil_val, index);
if (g->ops.ltc.set_zbc_s_entry != NULL) {
g->ops.ltc.set_zbc_s_entry(g, stencil_val, index);
}
/* update local copy */
gr->zbc_s_tbl[index].stencil = stencil_val->depth;
gr->zbc_s_tbl[index].format = stencil_val->format;
gr->zbc_s_tbl[index].ref_cnt++;
gk20a_writel(g, gr_gpcs_swdx_dss_zbc_s_r(index), stencil_val->depth);
zbc_s = gk20a_readl(g, gr_gpcs_swdx_dss_zbc_s_01_to_04_format_r() +
nvgpu_writel(g, gr_gpcs_swdx_dss_zbc_s_r(index), stencil_val->depth);
zbc_s = nvgpu_readl(g, gr_gpcs_swdx_dss_zbc_s_01_to_04_format_r() +
(index & ~3U));
zbc_s &= ~(U32(0x7f) << (index % 4U) * 7U);
zbc_s |= stencil_val->format << (index % 4U) * 7U;
gk20a_writel(g, gr_gpcs_swdx_dss_zbc_s_01_to_04_format_r() +
nvgpu_writel(g, gr_gpcs_swdx_dss_zbc_s_01_to_04_format_r() +
(index & ~3U), zbc_s);
return 0;
@@ -1273,7 +1275,7 @@ int gr_gv11b_load_stencil_tbl(struct gk20a *g, struct gr_gk20a *gr)
zbc_val.depth = s_tbl->stencil;
zbc_val.format = s_tbl->format;
ret = g->ops.gr.add_zbc_s(g, gr, &zbc_val, i);
ret = g->ops.gr.zbc.add_stencil(g, gr, &zbc_val, i);
if (ret != 0) {
return ret;
}

32
drivers/gpu/nvgpu/gv11b/hal_gv11b.c
View File

@@ -325,16 +325,6 @@ static const struct gpu_ops gv11b_ops = {
.is_tpc_addr = gr_gm20b_is_tpc_addr,
.get_tpc_num = gr_gm20b_get_tpc_num,
.detect_sm_arch = gr_gv11b_detect_sm_arch,
.add_zbc_color = gr_gp10b_add_zbc_color,
.add_zbc_depth = gr_gp10b_add_zbc_depth,
.get_gpcs_swdx_dss_zbc_c_format_reg =
gr_gv11b_get_gpcs_swdx_dss_zbc_c_format_reg,
.get_gpcs_swdx_dss_zbc_z_format_reg =
gr_gv11b_get_gpcs_swdx_dss_zbc_z_format_reg,
.zbc_set_table = gk20a_gr_zbc_set_table,
.zbc_query_table = gr_gk20a_query_zbc,
.pmu_save_zbc = gk20a_pmu_save_zbc,
.add_zbc = gr_gk20a_add_zbc,
.pagepool_default_size = gr_gv11b_pagepool_default_size,
.init_ctx_state = gr_gp10b_init_ctx_state,
.alloc_gr_ctx = gr_gk20a_alloc_gr_ctx,
@@ -415,19 +405,14 @@ static const struct gpu_ops gv11b_ops = {
.is_etpc_addr = gv11b_gr_pri_is_etpc_addr,
.egpc_etpc_priv_addr_table = gv11b_gr_egpc_etpc_priv_addr_table,
.handle_tpc_mpc_exception = gr_gv11b_handle_tpc_mpc_exception,
.zbc_s_query_table = gr_gv11b_zbc_s_query_table,
.load_zbc_s_default_tbl = gr_gv11b_load_stencil_default_tbl,
.handle_gpc_gpcmmu_exception =
gr_gv11b_handle_gpc_gpcmmu_exception,
.add_zbc_type_s = gr_gv11b_add_zbc_type_s,
.get_egpc_base = gv11b_gr_get_egpc_base,
.get_egpc_etpc_num = gv11b_gr_get_egpc_etpc_num,
.handle_gpc_gpccs_exception =
gr_gv11b_handle_gpc_gpccs_exception,
.load_zbc_s_tbl = gr_gv11b_load_stencil_tbl,
.access_smpc_reg = gv11b_gr_access_smpc_reg,
.is_egpc_addr = gv11b_gr_pri_is_egpc_addr,
.add_zbc_s = gr_gv11b_add_zbc_stencil,
.handle_gcc_exception = gr_gv11b_handle_gcc_exception,
.init_sw_veid_bundle = gr_gv11b_init_sw_veid_bundle,
.handle_tpc_sm_ecc_exception =
@@ -553,6 +538,23 @@ static const struct gpu_ops gv11b_ops = {
.get_pes_tpc_mask = gm20b_gr_config_get_pes_tpc_mask,
.get_pd_dist_skip_table_size =
gm20b_gr_config_get_pd_dist_skip_table_size,
},
.zbc = {
.add_color = gr_gp10b_add_zbc_color,
.add_depth = gr_gp10b_add_zbc_depth,
.set_table = gk20a_gr_zbc_set_table,
.query_table = gr_gk20a_query_zbc,
.pmu_save = gk20a_pmu_save_zbc,
.stencil_query_table = gr_gv11b_zbc_s_query_table,
.load_stencil_default_tbl =
gr_gv11b_load_stencil_default_tbl,
.add_type_stencil = gr_gv11b_add_zbc_type_s,
.load_stencil_tbl = gr_gv11b_load_stencil_tbl,
.add_stencil = gr_gv11b_add_zbc_stencil,
.get_gpcs_swdx_dss_zbc_c_format_reg =
gr_gv11b_get_gpcs_swdx_dss_zbc_c_format_reg,
.get_gpcs_swdx_dss_zbc_z_format_reg =
gr_gv11b_get_gpcs_swdx_dss_zbc_z_format_reg,
}
},
.fb = {

52
drivers/gpu/nvgpu/include/nvgpu/gk20a.h
View File

@@ -315,27 +315,6 @@ struct gpu_ops {
u32 (*get_tpc_num)(struct gk20a *g, u32 addr);
u32 (*get_egpc_base)(struct gk20a *g);
void (*detect_sm_arch)(struct gk20a *g);
int (*add_zbc_color)(struct gk20a *g, struct gr_gk20a *gr,
struct zbc_entry *color_val, u32 index);
int (*add_zbc_depth)(struct gk20a *g, struct gr_gk20a *gr,
struct zbc_entry *depth_val, u32 index);
int (*add_zbc_s)(struct gk20a *g, struct gr_gk20a *gr,
struct zbc_entry *s_val, u32 index);
int (*zbc_set_table)(struct gk20a *g, struct gr_gk20a *gr,
struct zbc_entry *zbc_val);
int (*zbc_query_table)(struct gk20a *g, struct gr_gk20a *gr,
struct zbc_query_params *query_params);
int (*zbc_s_query_table)(struct gk20a *g, struct gr_gk20a *gr,
struct zbc_query_params *query_params);
int (*load_zbc_s_default_tbl)(struct gk20a *g,
struct gr_gk20a *gr);
int (*load_zbc_s_tbl)(struct gk20a *g,
struct gr_gk20a *gr);
void (*pmu_save_zbc)(struct gk20a *g, u32 entries);
int (*add_zbc)(struct gk20a *g, struct gr_gk20a *gr,
struct zbc_entry *zbc_val);
bool (*add_zbc_type_s)(struct gk20a *g, struct gr_gk20a *gr,
struct zbc_entry *zbc_val, int *ret_val);
u32 (*pagepool_default_size)(struct gk20a *g);
int (*init_ctx_state)(struct gk20a *g);
int (*alloc_gr_ctx)(struct gk20a *g,
@@ -482,8 +461,6 @@ struct gpu_ops {
unsigned long (*get_max_gfxp_wfi_timeout_count)
(struct gk20a *g);
void (*ecc_init_scrub_reg)(struct gk20a *g);
u32 (*get_gpcs_swdx_dss_zbc_c_format_reg)(struct gk20a *g);
u32 (*get_gpcs_swdx_dss_zbc_z_format_reg)(struct gk20a *g);
void (*fecs_host_int_enable)(struct gk20a *g);
int (*handle_ssync_hww)(struct gk20a *g);
int (*handle_notify_pending)(struct gk20a *g,
@@ -632,6 +609,35 @@ struct gpu_ops {
u32 (*get_pd_dist_skip_table_size)(void);
} config;
struct {
int (*add_color)(struct gk20a *g, struct gr_gk20a *gr,
struct zbc_entry *color_val, u32 index);
int (*add_depth)(struct gk20a *g, struct gr_gk20a *gr,
struct zbc_entry *depth_val, u32 index);
int (*set_table)(struct gk20a *g, struct gr_gk20a *gr,
struct zbc_entry *zbc_val);
int (*query_table)(struct gk20a *g,
struct gr_gk20a *gr,
struct zbc_query_params *query_params);
int (*stencil_query_table)(struct gk20a *g,
struct gr_gk20a *gr,
struct zbc_query_params *query_params);
int (*load_stencil_default_tbl)(struct gk20a *g,
struct gr_gk20a *gr);
int (*load_stencil_tbl)(struct gk20a *g,
struct gr_gk20a *gr);
int (*add_stencil)(struct gk20a *g, struct gr_gk20a *gr,
struct zbc_entry *s_val, u32 index);
void (*pmu_save)(struct gk20a *g, u32 entries);
bool (*add_type_stencil)(struct gk20a *g,
struct gr_gk20a *gr,
struct zbc_entry *zbc_val, int *ret_val);
u32 (*get_gpcs_swdx_dss_zbc_c_format_reg)(
struct gk20a *g);
u32 (*get_gpcs_swdx_dss_zbc_z_format_reg)(
struct gk20a *g);
} zbc;
u32 (*fecs_falcon_base_addr)(void);
u32 (*gpccs_falcon_base_addr)(void);

4
drivers/gpu/nvgpu/os/linux/ioctl_ctrl.c
View File

@@ -1724,7 +1724,7 @@ long gk20a_ctrl_dev_ioctl(struct file *filp, unsigned int cmd, unsigned long arg
if (!err) {
err = gk20a_busy(g);
if (!err) {
err = g->ops.gr.zbc_set_table(g, &g->gr,
err = g->ops.gr.zbc.set_table(g, &g->gr,
zbc_val);
gk20a_idle(g);
}
@@ -1743,7 +1743,7 @@ long gk20a_ctrl_dev_ioctl(struct file *filp, unsigned int cmd, unsigned long arg
zbc_tbl->type = query_table_args->type;
zbc_tbl->index_size = query_table_args->index_size;
err = g->ops.gr.zbc_query_table(g, &g->gr, zbc_tbl);
err = g->ops.gr.zbc.query_table(g, &g->gr, zbc_tbl);
if (!err) {
switch (zbc_tbl->type) {

32
drivers/gpu/nvgpu/tu104/hal_tu104.c
View File

@@ -390,16 +390,6 @@ static const struct gpu_ops tu104_ops = {
.is_tpc_addr = gr_gm20b_is_tpc_addr,
.get_tpc_num = gr_gm20b_get_tpc_num,
.detect_sm_arch = gr_gv11b_detect_sm_arch,
.add_zbc_color = gr_gp10b_add_zbc_color,
.add_zbc_depth = gr_gp10b_add_zbc_depth,
.get_gpcs_swdx_dss_zbc_c_format_reg =
gr_gv11b_get_gpcs_swdx_dss_zbc_c_format_reg,
.get_gpcs_swdx_dss_zbc_z_format_reg =
gr_gv11b_get_gpcs_swdx_dss_zbc_z_format_reg,
.zbc_set_table = gk20a_gr_zbc_set_table,
.zbc_query_table = gr_gk20a_query_zbc,
.pmu_save_zbc = gk20a_pmu_save_zbc,
.add_zbc = gr_gk20a_add_zbc,
.pagepool_default_size = gr_gv11b_pagepool_default_size,
.init_ctx_state = gr_gp10b_init_ctx_state,
.alloc_gr_ctx = gr_gk20a_alloc_gr_ctx,
@@ -481,19 +471,14 @@ static const struct gpu_ops tu104_ops = {
.is_etpc_addr = gv11b_gr_pri_is_etpc_addr,
.egpc_etpc_priv_addr_table = gv11b_gr_egpc_etpc_priv_addr_table,
.handle_tpc_mpc_exception = gr_gv11b_handle_tpc_mpc_exception,
.zbc_s_query_table = gr_gv11b_zbc_s_query_table,
.load_zbc_s_default_tbl = gr_gv11b_load_stencil_default_tbl,
.handle_gpc_gpcmmu_exception =
gr_gv11b_handle_gpc_gpcmmu_exception,
.add_zbc_type_s = gr_gv11b_add_zbc_type_s,
.get_egpc_base = gv11b_gr_get_egpc_base,
.get_egpc_etpc_num = gv11b_gr_get_egpc_etpc_num,
.handle_gpc_gpccs_exception =
gr_gv11b_handle_gpc_gpccs_exception,
.load_zbc_s_tbl = gr_gv11b_load_stencil_tbl,
.access_smpc_reg = gv11b_gr_access_smpc_reg,
.is_egpc_addr = gv11b_gr_pri_is_egpc_addr,
.add_zbc_s = gr_gv11b_add_zbc_stencil,
.handle_gcc_exception = gr_gv11b_handle_gcc_exception,
.init_sw_veid_bundle = gr_gv11b_init_sw_veid_bundle,
.handle_tpc_sm_ecc_exception =
@@ -618,6 +603,23 @@ static const struct gpu_ops tu104_ops = {
.get_pes_tpc_mask = gm20b_gr_config_get_pes_tpc_mask,
.get_pd_dist_skip_table_size =
gm20b_gr_config_get_pd_dist_skip_table_size,
},
.zbc = {
.add_color = gr_gp10b_add_zbc_color,
.add_depth = gr_gp10b_add_zbc_depth,
.set_table = gk20a_gr_zbc_set_table,
.query_table = gr_gk20a_query_zbc,
.pmu_save = gk20a_pmu_save_zbc,
.stencil_query_table = gr_gv11b_zbc_s_query_table,
.load_stencil_default_tbl =
gr_gv11b_load_stencil_default_tbl,
.add_type_stencil = gr_gv11b_add_zbc_type_s,
.load_stencil_tbl = gr_gv11b_load_stencil_tbl,
.add_stencil = gr_gv11b_add_zbc_stencil,
.get_gpcs_swdx_dss_zbc_c_format_reg =
gr_gv11b_get_gpcs_swdx_dss_zbc_c_format_reg,
.get_gpcs_swdx_dss_zbc_z_format_reg =
gr_gv11b_get_gpcs_swdx_dss_zbc_z_format_reg,
}
},
.fb = {

20
drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c
View File

@@ -136,12 +136,6 @@ static const struct gpu_ops vgpu_gp10b_ops = {
.is_tpc_addr = gr_gm20b_is_tpc_addr,
.get_tpc_num = gr_gm20b_get_tpc_num,
.detect_sm_arch = vgpu_gr_detect_sm_arch,
.add_zbc_color = NULL,
.add_zbc_depth = NULL,
.zbc_set_table = vgpu_gr_add_zbc,
.zbc_query_table = vgpu_gr_query_zbc,
.pmu_save_zbc = NULL,
.add_zbc = NULL,
.pagepool_default_size = gr_gp10b_pagepool_default_size,
.init_ctx_state = vgpu_gr_gp10b_init_ctx_state,
.alloc_gr_ctx = vgpu_gr_alloc_gr_ctx,
@@ -305,6 +299,20 @@ static const struct gpu_ops vgpu_gp10b_ops = {
},
.config = {
.get_gpc_tpc_mask = vgpu_gr_get_gpc_tpc_mask,
},
.zbc = {
.add_color = NULL,
.add_depth = NULL,
.set_table = vgpu_gr_add_zbc,
.query_table = vgpu_gr_query_zbc,
.pmu_save = NULL,
.stencil_query_table = NULL,
.load_stencil_default_tbl = NULL,
.add_type_stencil = NULL,
.load_stencil_tbl = NULL,
.add_stencil = NULL,
.get_gpcs_swdx_dss_zbc_c_format_reg = NULL,
.get_gpcs_swdx_dss_zbc_z_format_reg = NULL,
}
},
.fb = {

26
drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c
View File

@@ -151,12 +151,6 @@ static const struct gpu_ops vgpu_gv11b_ops = {
.is_tpc_addr = gr_gm20b_is_tpc_addr,
.get_tpc_num = gr_gm20b_get_tpc_num,
.detect_sm_arch = vgpu_gr_detect_sm_arch,
.add_zbc_color = NULL,
.add_zbc_depth = NULL,
.zbc_set_table = vgpu_gr_add_zbc,
.zbc_query_table = vgpu_gr_query_zbc,
.pmu_save_zbc = NULL,
.add_zbc = NULL,
.pagepool_default_size = gr_gv11b_pagepool_default_size,
.init_ctx_state = vgpu_gr_gp10b_init_ctx_state,
.alloc_gr_ctx = vgpu_gr_alloc_gr_ctx,
@@ -232,19 +226,14 @@ static const struct gpu_ops vgpu_gv11b_ops = {
.is_etpc_addr = gv11b_gr_pri_is_etpc_addr,
.egpc_etpc_priv_addr_table = gv11b_gr_egpc_etpc_priv_addr_table,
.handle_tpc_mpc_exception = gr_gv11b_handle_tpc_mpc_exception,
.zbc_s_query_table = gr_gv11b_zbc_s_query_table,
.load_zbc_s_default_tbl = gr_gv11b_load_stencil_default_tbl,
.handle_gpc_gpcmmu_exception =
gr_gv11b_handle_gpc_gpcmmu_exception,
.add_zbc_type_s = gr_gv11b_add_zbc_type_s,
.get_egpc_base = gv11b_gr_get_egpc_base,
.get_egpc_etpc_num = gv11b_gr_get_egpc_etpc_num,
.handle_gpc_gpccs_exception =
gr_gv11b_handle_gpc_gpccs_exception,
.load_zbc_s_tbl = gr_gv11b_load_stencil_tbl,
.access_smpc_reg = gv11b_gr_access_smpc_reg,
.is_egpc_addr = gv11b_gr_pri_is_egpc_addr,
.add_zbc_s = gr_gv11b_add_zbc_stencil,
.handle_gcc_exception = gr_gv11b_handle_gcc_exception,
.init_sw_veid_bundle = gr_gv11b_init_sw_veid_bundle,
.handle_tpc_sm_ecc_exception =
@@ -350,6 +339,21 @@ static const struct gpu_ops vgpu_gv11b_ops = {
},
.config = {
.get_gpc_tpc_mask = vgpu_gr_get_gpc_tpc_mask,
},
.zbc = {
.add_color = NULL,
.add_depth = NULL,
.set_table = vgpu_gr_add_zbc,
.query_table = vgpu_gr_query_zbc,
.pmu_save = NULL,
.stencil_query_table = gr_gv11b_zbc_s_query_table,
.load_stencil_default_tbl =
gr_gv11b_load_stencil_default_tbl,
.add_type_stencil = gr_gv11b_add_zbc_type_s,
.load_stencil_tbl = gr_gv11b_load_stencil_tbl,
.add_stencil = gr_gv11b_add_zbc_stencil,
.get_gpcs_swdx_dss_zbc_c_format_reg = NULL,
.get_gpcs_swdx_dss_zbc_z_format_reg = NULL,
}
},
.fb = {