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gpu: nvgpu: resolve circular dependency between gr/config and priv_ring

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gr/config needs to get gpc_count from priv_ring, and priv_ring calls
API exposed by gr/config to get gpc_count in its ISR

priv_ring unit already has an HAL API to get gpc_count so it does not
need to rely on gr/config for same
Hence resolve the dependency by using g->ops.priv_ring.get_gpc_count()
instead of nvgpu_gr_config_get_gpc_count()

Jira NVGPU-1879

Change-Id: I1c894dac18dd9265f39375e930e8e9f9b0d67050
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2019147
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Deepak Nibade
2019-02-12 14:20:56 +05:30
committed by mobile promotions
parent adee60b3e1
commit 60402c78b3
2 changed files with 2 additions and 4 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
drivers/gpu/nvgpu/common/priv_ring/priv_ring_gm20b.c
View File

@@ -26,7 +26,6 @@
#include <nvgpu/enabled.h>
#include <nvgpu/io.h>
#include <nvgpu/utils.h>
#include <nvgpu/gr/config.h>
#include "priv_ring_gm20b.h"
@@ -81,7 +80,7 @@ void gm20b_priv_ring_isr(struct gk20a *g)
gk20a_readl(g, pri_ringstation_sys_priv_error_code_r()));
}
for (gpc = 0; gpc < nvgpu_gr_config_get_gpc_count(g->gr.config); gpc++) {
for (gpc = 0; gpc < g->ops.priv_ring.get_gpc_count(g); gpc++) {
if ((status1 & BIT32(gpc)) != 0U) {
nvgpu_log(g, gpu_dbg_intr, "GPC%u write error. ADR %08x WRDAT %08x INFO %08x, CODE %08x", gpc,
gk20a_readl(g, pri_ringstation_gpc_gpc0_priv_error_adr_r() + gpc * gpc_priv_stride),

3
drivers/gpu/nvgpu/common/priv_ring/priv_ring_gp10b.c
View File

@@ -27,7 +27,6 @@
#include <nvgpu/enabled.h>
#include <nvgpu/io.h>
#include <nvgpu/utils.h>
#include <nvgpu/gr/config.h>
#include <nvgpu/gk20a.h>
#include <nvgpu/hw/gp10b/hw_pri_ringmaster_gp10b.h>
@@ -158,7 +157,7 @@ void gp10b_priv_ring_isr(struct gk20a *g)
if (status1 != 0U) {
gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_PRIV_STRIDE);
for (gpc = 0; gpc < nvgpu_gr_config_get_gpc_count(g->gr.config); gpc++) {
for (gpc = 0; gpc < g->ops.priv_ring.get_gpc_count(g); gpc++) {
offset = gpc * gpc_stride;
if ((status1 & BIT32(gpc)) != 0U) {
error_info = gk20a_readl(g,