gpu: nvgpu: Reorg clk HAL initialization

Reorganize HAL initialization to remove inheritance and construct
the gpu_ops struct at compile time. This patch only covers the clk
and clk_arb sub-module of the gpu_ops struct.

Perform HAL function assignments in hal_gxxxx.c through the
population of a chip-specific copy of gpu_ops.

Jira NVGPU-74

Change-Id: I553353df836b187b8eac61e16b63080b570c96b8
Signed-off-by: Sunny He <suhe@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1511076
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>

drivers/gpu/nvgpu/gm20b/clk_gm20b.c

@@ -1389,7 +1389,7 @@ static int set_pll_freq(struct gk20a *g, int allow_slide)
 	return err;
 }
 
-static int gm20b_init_clk_support(struct gk20a *g)
+int gm20b_init_clk_support(struct gk20a *g)
 {
 	struct clk_gk20a *clk = &g->clk;
 	u32 err;
@@ -1427,7 +1427,7 @@ static int gm20b_init_clk_support(struct gk20a *g)
 	return err;
 }
 
-static int gm20b_suspend_clk_support(struct gk20a *g)
+int gm20b_suspend_clk_support(struct gk20a *g)
 {
 	int ret = 0;
 
@@ -1445,7 +1445,7 @@ static int gm20b_suspend_clk_support(struct gk20a *g)
 	return ret;
 }
 
-static int gm20b_clk_get_voltage(struct clk_gk20a *clk, u64 *val)
+int gm20b_clk_get_voltage(struct clk_gk20a *clk, u64 *val)
 {
 	struct gk20a *g = clk->g;
 	struct pll_parms *gpc_pll_params = gm20b_get_gpc_pll_parms();
@@ -1472,7 +1472,7 @@ static int gm20b_clk_get_voltage(struct clk_gk20a *clk, u64 *val)
 	return 0;
 }
 
-static int gm20b_clk_get_gpcclk_clock_counter(struct clk_gk20a *clk, u64 *val)
+int gm20b_clk_get_gpcclk_clock_counter(struct clk_gk20a *clk, u64 *val)
 {
 	struct gk20a *g = clk->g;
 	u32 clk_slowdown, clk_slowdown_save;
@@ -1593,16 +1593,3 @@ int gm20b_clk_get_pll_debug_data(struct gk20a *g,
 	nvgpu_mutex_release(&g->clk.clk_mutex);
 	return 0;
 }
-
-void gm20b_init_clk_ops(struct gpu_ops *gops)
-{
-	gops->clk.init_clk_support = gm20b_init_clk_support;
-	gops->clk.suspend_clk_support = gm20b_suspend_clk_support;
-#ifdef CONFIG_DEBUG_FS
-	gops->clk.init_debugfs = gm20b_clk_init_debugfs;
-#endif
-	gops->clk.get_voltage = gm20b_clk_get_voltage;
-	gops->clk.get_gpcclk_clock_counter = gm20b_clk_get_gpcclk_clock_counter;
-	gops->clk.pll_reg_write = gm20b_clk_pll_reg_write;
-	gops->clk.get_pll_debug_data = gm20b_clk_get_pll_debug_data;
-}

drivers/gpu/nvgpu/gm20b/clk_gm20b.h

@@ -50,8 +50,6 @@ struct nvgpu_clk_pll_debug_data {
 	u32 trim_sys_gpcpll_dvfs0_dfs_dc_offset;
 };
 
-void gm20b_init_clk_ops(struct gpu_ops *gops);
-
 int gm20b_init_clk_setup_sw(struct gk20a *g);
 
 int gm20b_clk_prepare(struct clk_gk20a *clk);
@@ -67,6 +65,14 @@ struct pll_parms *gm20b_get_gpc_pll_parms(void);
 int gm20b_clk_init_debugfs(struct gk20a *g);
 #endif
 
+int gm20b_clk_pll_reg_write(struct gk20a *g, u32 reg, u32 val);
+int gm20b_init_clk_support(struct gk20a *g);
+int gm20b_suspend_clk_support(struct gk20a *g);
+int gm20b_clk_get_voltage(struct clk_gk20a *clk, u64 *val);
+int gm20b_clk_get_gpcclk_clock_counter(struct clk_gk20a *clk, u64 *val);
+int gm20b_clk_get_pll_debug_data(struct gk20a *g,
+			struct nvgpu_clk_pll_debug_data *d);
+
 /* 1:1 match between post divider settings and divisor value */
 static inline u32 nvgpu_pl_to_div(u32 pl)
 {

drivers/gpu/nvgpu/gm20b/hal_gm20b.c

@@ -277,6 +277,17 @@ static const struct gpu_ops gm20b_ops = {
 		.init_therm_setup_hw = gm20b_init_therm_setup_hw,
 		.elcg_init_idle_filters = gk20a_elcg_init_idle_filters,
 	},
+	.clk = {
+		.init_clk_support = gm20b_init_clk_support,
+		.suspend_clk_support = gm20b_suspend_clk_support,
+#ifdef CONFIG_DEBUG_FS
+		.init_debugfs = gm20b_clk_init_debugfs,
+#endif
+		.get_voltage = gm20b_clk_get_voltage,
+		.get_gpcclk_clock_counter = gm20b_clk_get_gpcclk_clock_counter,
+		.pll_reg_write = gm20b_clk_pll_reg_write,
+		.get_pll_debug_data = gm20b_clk_get_pll_debug_data,
+	},
 	.regops = {
 		.get_global_whitelist_ranges =
 			gm20b_get_global_whitelist_ranges,
@@ -373,6 +384,18 @@ int gm20b_init_hal(struct gk20a *g)
 	gops->fifo = gm20b_ops.fifo;
 	gops->gr_ctx = gm20b_ops.gr_ctx;
 	gops->therm = gm20b_ops.therm;
+	/*
+	 * clk must be assigned member by member
+	 * since some clk ops are assigned during probe prior to HAL init
+	 */
+	gops->clk.init_clk_support = gm20b_ops.clk.init_clk_support;
+	gops->clk.suspend_clk_support = gm20b_ops.clk.suspend_clk_support;
+	gops->clk.get_voltage = gm20b_ops.clk.get_voltage;
+	gops->clk.get_gpcclk_clock_counter =
+		gm20b_ops.clk.get_gpcclk_clock_counter;
+	gops->clk.pll_reg_write = gm20b_ops.clk.pll_reg_write;
+	gops->clk.get_pll_debug_data = gm20b_ops.clk.get_pll_debug_data;
+
 	gops->regops = gm20b_ops.regops;
 	gops->mc = gm20b_ops.mc;
 	gops->dbg_session_ops = gm20b_ops.dbg_session_ops;
@@ -427,7 +450,6 @@ int gm20b_init_hal(struct gk20a *g)
 	gm20b_init_fb(gops);
 	gm20b_init_mm(gops);
 	gm20b_init_pmu_ops(g);
-	gm20b_init_clk_ops(gops);
 
 	g->name = "gm20b";
 

drivers/gpu/nvgpu/gp106/clk_arb_gp106.c

@@ -16,13 +16,13 @@
 #include "clk/clk_arb.h"
 #include "clk_arb_gp106.h"
 
-static u32 gp106_get_arbiter_clk_domains(struct gk20a *g)
+u32 gp106_get_arbiter_clk_domains(struct gk20a *g)
 {
 	(void)g;
 	return (CTRL_CLK_DOMAIN_MCLK|CTRL_CLK_DOMAIN_GPC2CLK);
 }
 
-static int gp106_get_arbiter_clk_range(struct gk20a *g, u32 api_domain,
+int gp106_get_arbiter_clk_range(struct gk20a *g, u32 api_domain,
 		u16 *min_mhz, u16 *max_mhz)
 {
 	enum nv_pmu_clk_clkwhich clkwhich;
@@ -68,7 +68,7 @@ static int gp106_get_arbiter_clk_range(struct gk20a *g, u32 api_domain,
 	return 0;
 }
 
-static int gp106_get_arbiter_clk_default(struct gk20a *g, u32 api_domain,
+int gp106_get_arbiter_clk_default(struct gk20a *g, u32 api_domain,
 		u16 *default_mhz)
 {
 	enum nv_pmu_clk_clkwhich clkwhich;
@@ -96,11 +96,3 @@ static int gp106_get_arbiter_clk_default(struct gk20a *g, u32 api_domain,
 
 	return 0;
 }
-
-void gp106_init_clk_arb_ops(struct gpu_ops *gops)
-{
-	gops->clk_arb.get_arbiter_clk_domains = gp106_get_arbiter_clk_domains;
-	gops->clk_arb.get_arbiter_clk_range = gp106_get_arbiter_clk_range;
-	gops->clk_arb.get_arbiter_clk_default = gp106_get_arbiter_clk_default;
-	gops->clk_arb.get_current_pstate = nvgpu_clk_arb_get_current_pstate;
-}

drivers/gpu/nvgpu/gp106/clk_arb_gp106.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2016-2017, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -16,6 +16,10 @@
 #ifndef CLK_ARB_GP106_H
 #define CLK_ARB_GP106_H
 
-void gp106_init_clk_arb_ops(struct gpu_ops *gops);
+u32 gp106_get_arbiter_clk_domains(struct gk20a *g);
+int gp106_get_arbiter_clk_range(struct gk20a *g, u32 api_domain,
+		u16 *min_mhz, u16 *max_mhz);
+int gp106_get_arbiter_clk_default(struct gk20a *g, u32 api_domain,
+		u16 *default_mhz);
 
 #endif /* CLK_ARB_GP106_H */

drivers/gpu/nvgpu/gp106/clk_gp106.c

@@ -47,12 +47,12 @@ static int clk_gp106_debugfs_init(struct gk20a *g);
 
 
 static u32 gp106_get_rate_cntr(struct gk20a *g, struct namemap_cfg *);
-static u32 gp106_crystal_clk_hz(struct gk20a *g)
+u32 gp106_crystal_clk_hz(struct gk20a *g)
 {
 	return (XTAL4X_KHZ * 1000);
 }
 
-static unsigned long gp106_clk_measure_freq(struct gk20a *g, u32 api_domain)
+unsigned long gp106_clk_measure_freq(struct gk20a *g, u32 api_domain)
 {
 	struct clk_gk20a *clk = &g->clk;
 	u32 freq_khz;
@@ -76,7 +76,8 @@ static unsigned long gp106_clk_measure_freq(struct gk20a *g, u32 api_domain)
 	return freq_khz * 1000UL;
 }
 
-static int gp106_init_clk_support(struct gk20a *g) {
+int gp106_init_clk_support(struct gk20a *g)
+{
 	struct clk_gk20a *clk = &g->clk;
 	u32 err = 0;
 
@@ -273,18 +274,8 @@ err_out:
 }
 #endif /* CONFIG_DEBUG_FS */
 
-static int gp106_suspend_clk_support(struct gk20a *g)
+int gp106_suspend_clk_support(struct gk20a *g)
 {
 	nvgpu_mutex_destroy(&g->clk.clk_mutex);
 	return 0;
 }
-
-void gp106_init_clk_ops(struct gpu_ops *gops) {
-	gops->clk.init_clk_support = gp106_init_clk_support;
-	gops->clk.get_crystal_clk_hz = gp106_crystal_clk_hz;
-	gops->clk.measure_freq = gp106_clk_measure_freq;
-	gops->clk.suspend_clk_support = gp106_suspend_clk_support;
-	gops->clk.mclk_init = gp106_mclk_init;
-	gops->clk.mclk_change = gp106_mclk_change;
-	gops->clk.mclk_deinit = gp106_mclk_deinit;
-}

drivers/gpu/nvgpu/gp106/clk_gp106.h

@@ -51,6 +51,9 @@ struct namemap_cfg {
 	char name[24];
 };
 
-void gp106_init_clk_ops(struct gpu_ops *gops);
+int gp106_init_clk_support(struct gk20a *g);
+u32 gp106_crystal_clk_hz(struct gk20a *g);
+unsigned long gp106_clk_measure_freq(struct gk20a *g, u32 api_domain);
+int gp106_suspend_clk_support(struct gk20a *g);
 
 #endif /* CLK_GP106_H */

drivers/gpu/nvgpu/gp106/hal_gp106.c

@@ -46,6 +46,7 @@
 
 #include "gp106/clk_gp106.h"
 #include "gp106/clk_arb_gp106.h"
+#include "gp106/mclk_gp106.h"
 #include "gm206/bios_gm206.h"
 #include "gp106/therm_gp106.h"
 #include "gp106/xve_gp106.h"
@@ -72,6 +73,7 @@
 #include <nvgpu/hw/gp106/hw_top_gp106.h>
 #include <nvgpu/hw/gp106/hw_pram_gp106.h>
 
+
 static int gp106_get_litter_value(struct gk20a *g, int value)
 {
 	int ret = -EINVAL;
@@ -353,6 +355,21 @@ static const struct gpu_ops gp106_ops = {
 		.get_internal_sensor_limits = gp106_get_internal_sensor_limits,
 		.configure_therm_alert = gp106_configure_therm_alert,
 	},
+	.clk = {
+		.init_clk_support = gp106_init_clk_support,
+		.get_crystal_clk_hz = gp106_crystal_clk_hz,
+		.measure_freq = gp106_clk_measure_freq,
+		.suspend_clk_support = gp106_suspend_clk_support,
+		.mclk_init = gp106_mclk_init,
+		.mclk_change = gp106_mclk_change,
+		.mclk_deinit = gp106_mclk_deinit,
+	},
+	.clk_arb = {
+		.get_arbiter_clk_domains = gp106_get_arbiter_clk_domains,
+		.get_arbiter_clk_range = gp106_get_arbiter_clk_range,
+		.get_arbiter_clk_default = gp106_get_arbiter_clk_default,
+		.get_current_pstate = nvgpu_clk_arb_get_current_pstate,
+	},
 	.regops = {
 		.get_global_whitelist_ranges =
 			gp106_get_global_whitelist_ranges,
@@ -470,6 +487,19 @@ int gp106_init_hal(struct gk20a *g)
 	gops->fecs_trace = gp106_ops.fecs_trace;
 	gops->pramin = gp106_ops.pramin;
 	gops->therm = gp106_ops.therm;
+	/*
+	 * clk must be assigned member by member
+	 * since some clk ops are assigned during probe prior to HAL init
+	 */
+	gops->clk.init_clk_support = gp106_ops.clk.init_clk_support;
+	gops->clk.get_crystal_clk_hz = gp106_ops.clk.get_crystal_clk_hz;
+	gops->clk.measure_freq = gp106_ops.clk.measure_freq;
+	gops->clk.suspend_clk_support = gp106_ops.clk.suspend_clk_support;
+	gops->clk.mclk_init = gp106_ops.clk.mclk_init;
+	gops->clk.mclk_change = gp106_ops.clk.mclk_change;
+	gops->clk.mclk_deinit = gp106_ops.clk.mclk_deinit;
+
+	gops->clk_arb = gp106_ops.clk_arb;
 	gops->regops = gp106_ops.regops;
 	gops->mc = gp106_ops.mc;
 	gops->debug = gp106_ops.debug;
@@ -499,8 +529,6 @@ int gp106_init_hal(struct gk20a *g)
 	gp106_init_fb(gops);
 	gp106_init_mm(gops);
 	gp106_init_pmu_ops(g);
-	gp106_init_clk_ops(gops);
-	gp106_init_clk_arb_ops(gops);
 
 	g->name = "gp10x";