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gpu: nvgpu: isolate common & hal falcon_set_irq functions

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nvgpu_falcon_set_irq should handle interrupts state. gk20a_falcon_set_irq
is supposed to be hal API that will enable/disable the falcon interrupts.

JIRA NVGPU-1459

Change-Id: I2c97a7c1fd5cc0a5d11d80f62bca5aaa66f3b3c9
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2015591
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Sagar Kamble
2019-02-06 15:10:14 +05:30
committed by mobile promotions
parent b6b56bd556
commit 11fa89d618
2 changed files with 14 additions and 12 deletions
Download Patch File Download Diff File Expand all files Collapse all files

19
drivers/gpu/nvgpu/common/falcon/falcon.c
View File

@@ -140,19 +140,28 @@ void nvgpu_falcon_set_irq(struct nvgpu_falcon *flcn, bool enable,
u32 intr_mask, u32 intr_dest)
{
struct nvgpu_falcon_ops *flcn_ops;
struct gk20a *g;
if (flcn == NULL) {
return;
}
g = flcn->g;
flcn_ops = &flcn->flcn_ops;
if (flcn_ops->set_irq != NULL) {
flcn_ops->set_irq(flcn, enable, intr_mask, intr_dest);
} else {
nvgpu_warn(flcn->g, "Invalid op on falcon 0x%x ",
flcn->flcn_id);
if (flcn_ops->set_irq == NULL) {
nvgpu_warn(g, "Invalid op on falcon 0x%x ", flcn->flcn_id);
return;
}
if (!flcn->is_interrupt_enabled) {
nvgpu_warn(g, "Interrupt not supported on flcn 0x%x ",
flcn->flcn_id);
/* Keep interrupt disabled */
enable = false;
}
flcn_ops->set_irq(flcn, enable, intr_mask, intr_dest);
}
int nvgpu_falcon_wait_for_halt(struct nvgpu_falcon *flcn, unsigned int timeout)

7
drivers/gpu/nvgpu/common/falcon/falcon_gk20a.c
View File

@@ -68,13 +68,6 @@ static void gk20a_falcon_set_irq(struct nvgpu_falcon *flcn, bool enable,
struct gk20a *g = flcn->g;
u32 base_addr = flcn->flcn_base;
if (!flcn->is_interrupt_enabled) {
nvgpu_warn(g, "Interrupt not supported on flcn 0x%x ",
flcn->flcn_id);
/* Keep interrupt disabled */
enable = false;
}
if (enable) {
gk20a_writel(g, base_addr + falcon_falcon_irqmset_r(),
intr_mask);