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gpu: nvgpu: isolate common & hal falcon_reset functions

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nvgpu_falcon_reset should handle engine specific falcon reset or resort to
falcon CPU reset. gk20a_falcon_reset is supposed to be hal API that will
reset the falcon CPU. Hence move the dependent engine reset to
nvgpu_falcon_reset.

JIRA NVGPU-1459

Change-Id: I1b15f31a8bbb515736af5b0122ce206be0811bbc
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2015590
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Sagar Kamble
2019-02-06 14:57:06 +05:30
committed by mobile promotions
parent 69dd2ce8be
commit b6b56bd556
3 changed files with 19 additions and 22 deletions
Download Patch File Download Diff File Expand all files Collapse all files

19
drivers/gpu/nvgpu/common/falcon/falcon.c
View File

@@ -109,25 +109,30 @@ exit:
int nvgpu_falcon_reset(struct nvgpu_falcon *flcn)
{
struct nvgpu_falcon_ops *flcn_ops;
struct gk20a *g;
int status = 0;
if (flcn == NULL) {
return -EINVAL;
}
g = flcn->g;
flcn_ops = &flcn->flcn_ops;
if (flcn_ops->reset != NULL) {
status = flcn_ops->reset(flcn);
if (status == 0) {
status = nvgpu_falcon_mem_scrub_wait(flcn);
}
if (flcn->flcn_engine_dep_ops.reset_eng != NULL) {
/* falcon & engine reset */
status = flcn->flcn_engine_dep_ops.reset_eng(g);
} else if (flcn_ops->reset != NULL) {
flcn_ops->reset(flcn);
} else {
nvgpu_warn(flcn->g, "Invalid op on falcon 0x%x ",
flcn->flcn_id);
nvgpu_warn(g, "Invalid op on falcon 0x%x ", flcn->flcn_id);
status = -EINVAL;
}
if (status == 0) {
status = nvgpu_falcon_mem_scrub_wait(flcn);
}
return status;
}

20
drivers/gpu/nvgpu/common/falcon/falcon_gk20a.c
View File

@@ -28,25 +28,17 @@
#include <nvgpu/hw/gm20b/hw_falcon_gm20b.h>
static int gk20a_falcon_reset(struct nvgpu_falcon *flcn)
static void gk20a_falcon_reset(struct nvgpu_falcon *flcn)
{
struct gk20a *g = flcn->g;
u32 base_addr = flcn->flcn_base;
u32 unit_status = 0;
int status = 0;
if (flcn->flcn_engine_dep_ops.reset_eng != NULL) {
/* falcon & engine reset */
status = flcn->flcn_engine_dep_ops.reset_eng(g);
} else {
/* do falcon CPU hard reset */
unit_status = gk20a_readl(g, base_addr +
falcon_falcon_cpuctl_r());
gk20a_writel(g, base_addr + falcon_falcon_cpuctl_r(),
(unit_status | falcon_falcon_cpuctl_hreset_f(1)));
}
return status;
/* do falcon CPU hard reset */
unit_status = gk20a_readl(g, base_addr +
falcon_falcon_cpuctl_r());
gk20a_writel(g, base_addr + falcon_falcon_cpuctl_r(),
(unit_status | falcon_falcon_cpuctl_hreset_f(1)));
}
static bool gk20a_falcon_clear_halt_interrupt_status(struct nvgpu_falcon *flcn)

2
drivers/gpu/nvgpu/common/falcon/falcon_priv.h
View File

@@ -173,7 +173,7 @@ struct nvgpu_falcon_engine_dependency_ops {
};
struct nvgpu_falcon_ops {
int (*reset)(struct nvgpu_falcon *flcn);
void (*reset)(struct nvgpu_falcon *flcn);
void (*set_irq)(struct nvgpu_falcon *flcn, bool enable,
u32 intr_mask, u32 intr_dest);
bool (*clear_halt_interrupt_status)(struct nvgpu_falcon *flcn);