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gpu: nvgpu: determine memory configuration in hal

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Remove mem_config_idx from platform data, and instead let
HAL determine which memory configuration to use. For this
purpose, HAL may use PCI device identifiers, VBIOS version
and possibly RAMCFG strap register.

Bug 1929155

Change-Id: I9fcd67ff407382839ff81470789043fae1c81283
Reviewed-on: http://git-master/r/1497813
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
(cherry picked from commit 3f722945213bacfc5f6707059b9baccebd92cef1)
Reviewed-on: https://git-master/r/1506583
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
This commit is contained in:
Thomas Fleury
2017-06-07 11:31:54 -07:00
committed by mobile promotions
parent 28093a374b
commit 125c770c2a
3 changed files with 2 additions and 15 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
drivers/gpu/nvgpu/common/linux/pci.c
View File

@@ -96,7 +96,6 @@ static struct gk20a_platform nvgpu_pci_device[] = {
.ina3221_dcb_index = 0,
.ina3221_i2c_address = 0x84,
.ina3221_i2c_port = 0x2,
.mem_config_idx = GP106_MEM_CONFIG_GDDR5_PG418,
},
{ /* DEVICE=0x1c36 */
/* ptimer src frequency in hz */
@@ -132,7 +131,6 @@ static struct gk20a_platform nvgpu_pci_device[] = {
.ina3221_dcb_index = 0,
.ina3221_i2c_address = 0x84,
.ina3221_i2c_port = 0x2,
.mem_config_idx = GP106_MEM_CONFIG_GDDR5_PG418,
},
{ /* DEVICE=0x1c37 */
/* ptimer src frequency in hz */
@@ -168,7 +166,6 @@ static struct gk20a_platform nvgpu_pci_device[] = {
.ina3221_dcb_index = 0,
.ina3221_i2c_address = 0x84,
.ina3221_i2c_port = 0x2,
.mem_config_idx = GP106_MEM_CONFIG_GDDR5_PG418,
},
{ /* DEVICE=0x1c75 */
/* ptimer src frequency in hz */
@@ -204,7 +201,6 @@ static struct gk20a_platform nvgpu_pci_device[] = {
.ina3221_dcb_index = 1,
.ina3221_i2c_address = 0x80,
.ina3221_i2c_port = 0x1,
.mem_config_idx = GP106_MEM_CONFIG_GDDR5_PG419,
}
};
@@ -403,8 +399,6 @@ static int nvgpu_pci_probe(struct pci_dev *pdev,
g->msi_enabled = true;
#endif
g->mem_config_idx = platform->mem_config_idx;
g->irq_stall = pdev->irq;
g->irq_nonstall = pdev->irq;
if (g->irq_stall < 0)

3
drivers/gpu/nvgpu/gk20a/platform_gk20a.h
View File

@@ -235,9 +235,6 @@ struct gk20a_platform {
u32 ina3221_dcb_index;
u32 ina3221_i2c_address;
u32 ina3221_i2c_port;
/* memory training pattern and mclk switch sequences */
u8 mem_config_idx;
};
static inline struct gk20a_platform *gk20a_get_platform(

6
drivers/gpu/nvgpu/gm206/bios_gm206.c
View File

@@ -315,15 +315,11 @@ int gm206_bios_init(struct gk20a *g)
return -EINVAL;
}
/* WAR for HW2.5 RevA (identified by VBIOS version)
* - INA3221 is missing
* - use PG418 MCLK switching sequences
*/
/* WAR for HW2.5 RevA (INA3221 is missing) */
if ((g->pci_vendor_id == PCI_VENDOR_ID_NVIDIA) &&
(g->pci_device_id == 0x1c75) &&
(g->gpu_characteristics.vbios_version == 0x86065300)) {
g->power_sensor_missing = true;
g->mem_config_idx = GP106_MEM_CONFIG_GDDR5_PG418;
}
#ifdef CONFIG_DEBUG_FS