gpu: nvgpu: vgpu: add t19x support

- add commit_inst hal ops
- add t19x cmds to cmd big union
- add t19x vgpu driver and call t19x hal init
- get guest channel_base to calculate hw channel id

Jira VFND-3796

Change-Id: Ic2431233fd174afc2c84c4794e20552e6e88b1dc
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: https://git-master/r/1474715
GVS: Gerrit_Virtual_Submit
Reviewed-by: Aingara Paramakuru <aparamakuru@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>

drivers/gpu/nvgpu/common/linux/module.c

@@ -41,6 +41,9 @@
 #include "intr.h"
 #ifdef CONFIG_TEGRA_19x_GPU
 #include "nvgpu_gpuid_t19x.h"
+#ifdef CONFIG_TEGRA_GR_VIRTUALIZATION
+#include "vgpu/vgpu_t19x.h"
+#endif
 #endif
 #include "os_linux.h"
 
@@ -242,6 +245,10 @@ static struct of_device_id tegra_gk20a_of_match[] = {
 #ifdef CONFIG_TEGRA_19x_GPU
 	{ .compatible = TEGRA_19x_GPU_COMPAT_TEGRA,
 		.data = &t19x_gpu_tegra_platform },
+#ifdef CONFIG_TEGRA_GR_VIRTUALIZATION
+	{ .compatible = TEGRA_19x_VGPU_COMPAT_TEGRA,
+		.data = &t19x_vgpu_tegra_platform },
+#endif
 #endif
 #ifdef CONFIG_TEGRA_GR_VIRTUALIZATION
 	{ .compatible = "nvidia,tegra124-gk20a-vgpu",

drivers/gpu/nvgpu/vgpu/fifo_vgpu.c

@@ -325,6 +325,8 @@ static int vgpu_init_fifo_setup_sw(struct gk20a *g)
 	f->deferred_reset_pending = false;
 	nvgpu_mutex_init(&f->deferred_reset_mutex);
 
+	f->channel_base = priv->constants.channel_base;
+
 	f->sw_ready = true;
 
 	gk20a_dbg_fn("done");

drivers/gpu/nvgpu/vgpu/gr_vgpu.c

@@ -35,7 +35,7 @@ static void vgpu_gr_detect_sm_arch(struct gk20a *g)
 			priv->constants.sm_arch_warp_count;
 }
 
-static int vgpu_gr_commit_inst(struct channel_gk20a *c, u64 gpu_va)
+int vgpu_gr_commit_inst(struct channel_gk20a *c, u64 gpu_va)
 {
 	struct tegra_vgpu_cmd_msg msg;
 	struct tegra_vgpu_ch_ctx_params *p = &msg.params.ch_ctx;
@@ -422,6 +422,8 @@ static void vgpu_gr_free_channel_ctx(struct channel_gk20a *c)
 {
 	gk20a_dbg_fn("");
 
+	if (c->g->ops.fifo.free_channel_ctx_header)
+		c->g->ops.fifo.free_channel_ctx_header(c);
 	vgpu_gr_unmap_global_ctx_buffers(c);
 	vgpu_gr_free_channel_patch_ctx(c);
 	vgpu_gr_free_channel_pm_ctx(c);
@@ -551,7 +553,7 @@ static int vgpu_gr_alloc_obj_ctx(struct channel_gk20a  *c,
 	}
 
 	/* commit gr ctx buffer */
-	err = vgpu_gr_commit_inst(c, ch_ctx->gr_ctx->mem.gpu_va);
+	err = g->ops.gr.commit_inst(c, ch_ctx->gr_ctx->mem.gpu_va);
 	if (err) {
 		nvgpu_err(g, "fail to commit gr ctx buffer");
 		goto out;
@@ -1227,6 +1229,7 @@ void vgpu_init_gr_ops(struct gpu_ops *gops)
 	gops->gr.clear_sm_error_state = vgpu_gr_clear_sm_error_state;
 	gops->gr.suspend_contexts = vgpu_gr_suspend_contexts;
 	gops->gr.resume_contexts = vgpu_gr_resume_contexts;
+	gops->gr.commit_inst = vgpu_gr_commit_inst;
 	gops->gr.dump_gr_regs = NULL;
 	gops->gr.set_boosted_ctx = NULL;
 	gops->gr.update_boosted_ctx = NULL;

drivers/gpu/nvgpu/vgpu/gr_vgpu.h

@@ -0,0 +1,19 @@
+/*
+ * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ */
+
+#ifndef _GR_VGPU_H_
+#define _GR_VGPU_H_
+
+int vgpu_gr_commit_inst(struct channel_gk20a *c, u64 gpu_va);
+
+#endif

drivers/gpu/nvgpu/vgpu/vgpu.c

@@ -24,6 +24,7 @@
 #include <nvgpu/enabled.h>
 #include <nvgpu/debug.h>
 #include <nvgpu/bus.h>
+#include <nvgpu/soc.h>
 
 #include "vgpu/vgpu.h"
 #include "vgpu/fecs_trace_vgpu.h"
@@ -38,6 +39,11 @@
 #include "common/linux/module.h"
 #include "common/linux/os_linux.h"
 
+#ifdef CONFIG_TEGRA_19x_GPU
+#include <vgpu/vgpu_t19x.h>
+#include <nvgpu_gpuid_t19x.h>
+#endif
+
 #include <nvgpu/hw/gk20a/hw_mc_gk20a.h>
 
 static inline int vgpu_comm_init(struct platform_device *pdev)
@@ -268,14 +274,14 @@ static int vgpu_init_support(struct platform_device *pdev)
 		goto fail;
 	}
 
-	regs = devm_ioremap_resource(&pdev->dev, r);
-	if (IS_ERR(regs)) {
-		dev_err(dev_from_gk20a(g), "failed to remap gk20a regs\n");
-		err = PTR_ERR(g->bar1);
-		goto fail;
-	}
-
 	if (r->name && !strcmp(r->name, "/vgpu")) {
+		regs = devm_ioremap_resource(&pdev->dev, r);
+		if (IS_ERR(regs)) {
+			dev_err(dev_from_gk20a(g),
+				"failed to remap gk20a regs\n");
+			err = PTR_ERR(regs);
+			goto fail;
+		}
 		g->bar1 = regs;
 		g->bar1_mem = r;
 	}
@@ -458,6 +464,11 @@ static int vgpu_init_hal(struct gk20a *g)
 		gk20a_dbg_info("gp10b detected");
 		err = vgpu_gp10b_init_hal(g);
 		break;
+#ifdef CONFIG_TEGRA_19x_GPU
+	case TEGRA_19x_GPUID:
+		err = vgpu_t19x_init_hal(g);
+		break;
+#endif
 	default:
 		nvgpu_err(g, "no support for %x", ver);
 		err = -ENODEV;
@@ -581,6 +592,9 @@ static int vgpu_pm_init(struct device *dev)
 
 	gk20a_dbg_fn("");
 
+	if (nvgpu_platform_is_simulation(g))
+		return 0;
+
 	__pm_runtime_disable(dev, false);
 
 	if (IS_ENABLED(CONFIG_GK20A_DEVFREQ))

include/linux/tegra_vgpu.h

@@ -21,6 +21,10 @@
 
 #include <nvgpu/types.h>
 
+#ifdef CONFIG_TEGRA_19x_GPU
+#include <linux/tegra_vgpu_t19x.h>
+#endif
+
 enum {
 	TEGRA_VGPU_MODULE_GPU = 0,
 };
@@ -454,6 +458,7 @@ struct tegra_vgpu_constants_params {
 	u8 force_preempt_mode;
 	u32 default_timeslice_us;
 	u32 preempt_ctx_size;
+	u32 channel_base;
 };
 
 struct tegra_vgpu_channel_cyclestats_snapshot_params {
@@ -555,6 +560,9 @@ struct tegra_vgpu_cmd_msg {
 		struct tegra_vgpu_perfbuf_mgt_params perfbuf_management;
 		struct tegra_vgpu_get_timestamps_zipper_params get_timestamps_zipper;
 		struct tegra_vgpu_get_gpu_freq_table_params get_gpu_freq_table;
+#ifdef CONFIG_TEGRA_19x_GPU
+		union tegra_vgpu_t19x_params t19x;
+#endif
 		char padding[192];
 	} params;
 };