gpu: nvgpu: unit: add MASTER, CCSR and PBDMA reg spaces

Browse Source

Added pre-populated register spaces for gv11b:
- NV_PCCSR 0x0080FFFF:0x00800000
- NV_PMC 0x00000FFF:0x00000000
- NV_PPBDMA 0x0005FFFF:0x00040000

Registers values were captured for Xavier on DDPX platform,
using reg_dump, after disabling railgating and ELPG.

Also added missing reg space unregistration for NV_TOP.

Jira NVGPU-3476

Change-Id: I8745f820819c1201846472602d7ef1872583ef4e
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2120657
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

...

This commit is contained in:

Thomas Fleury

2019-05-16 17:22:36 -07:00

committed by mobile promotions

parent 20d611b081

commit 12db97bd5c

1 changed files with 13170 additions and 576 deletions

Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL

Download Patch File Download Diff File Expand all files Collapse all files

13746

userspace/units/fifo/nvgpu-fifo-gv11b.c

File diff suppressed because it is too large Load Diff