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12db97bd5c
Added pre-populated register spaces for gv11b: - NV_PCCSR 0x0080FFFF:0x00800000 - NV_PMC 0x00000FFF:0x00000000 - NV_PPBDMA 0x0005FFFF:0x00040000 Registers values were captured for Xavier on DDPX platform, using reg_dump, after disabling railgating and ELPG. Also added missing reg space unregistration for NV_TOP. Jira NVGPU-3476 Change-Id: I8745f820819c1201846472602d7ef1872583ef4e Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2120657 GVS: Gerrit_Virtual_Submit Reviewed-by: Seema Khowala <seemaj@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>