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gpu: nvgpu: posix: update align macros for CERT-C

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The ALIGN() and ALIGN_MASK() macros were causing INT30 CERT-C
violations because of possible wrap issues. Update the macros to check
for potential wrap cases.

JIRA NVGPU-3515

Change-Id: I2af50fe036e8fcaf27e484af134c4a54fa4d19a1
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2124998
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Philip Elcan
2019-05-24 09:52:30 -04:00
committed by mobile promotions
parent 3f05901828
commit 1d1acaaa5e
1 changed files with 17 additions and 2 deletions
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19
drivers/gpu/nvgpu/include/nvgpu/posix/types.h
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@@ -115,8 +115,23 @@ typedef signed long long s64;
#define roundup(x, y) round_up(x, y)
#define round_down(x, y) ((x) & ~round_mask(x, y))
#define ALIGN_MASK(x, mask) (((x) + (mask)) & ~(mask))
#define ALIGN(x, a) ALIGN_MASK(x, (typeof(x))(a) - 1U)
#define ALIGN_MASK(x, mask) \
({ \
typeof(x) ret; \
typeof(x) sum = (x) + (mask); \
\
if ((sum >= (x)) && (sum >= (mask))) { \
ret = sum & ~(mask); \
} else { \
ret = (typeof(x))~(typeof(x))0 & ~(mask); \
} \
ret; \
})
#define ALIGN(x, a) ALIGN_MASK(x, \
(a) > (typeof(a))0 ? \
(typeof(x))(a) - 1U : \
(typeof(x))0)
#define PAGE_ALIGN(x) ALIGN(x, PAGE_SIZE)
#define HZ_TO_KHZ(x) ((x) / KHZ)