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gpu: nvgpu: add g cross reference in boardobjgrp

Browse Source 
Added a pointer to GPU context in boardobjgrp, and updated
constructors. It will be useful to free allocated DMA resources.

JIRA EVLR-1959
Bug 200352099

Change-Id: I006e4f970c9a2525dabdfd6ad417be64e36b7b68
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1586551
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Thomas Fleury
2017-10-23 15:52:00 -07:00
committed by mobile promotions
parent 8bdce5337e
commit 13093eff52
23 changed files with 50 additions and 39 deletions
Download Patch File Download Diff File Expand all files Collapse all files

15
drivers/gpu/nvgpu/boardobj/boardobjgrp.c
View File

@@ -44,7 +44,7 @@ struct boardobjgrp_pmucmdhandler_params {
u32 success;
};
u32 boardobjgrp_construct_super(struct boardobjgrp *pboardobjgrp)
u32 boardobjgrp_construct_super(struct gk20a *g, struct boardobjgrp *pboardobjgrp)
{
gk20a_dbg_info("");
@@ -57,6 +57,7 @@ u32 boardobjgrp_construct_super(struct boardobjgrp *pboardobjgrp)
if (pboardobjgrp->mask == NULL)
return -EINVAL;
pboardobjgrp->g = g;
pboardobjgrp->objmask = 0;
pboardobjgrp->classid = 0;
@@ -104,6 +105,7 @@ u32 boardobjgrp_destruct_impl(struct boardobjgrp *pboardobjgrp)
u32 boardobjgrp_destruct_super(struct boardobjgrp *pboardobjgrp)
{
struct boardobj *pboardobj;
struct gk20a *g = pboardobjgrp->g;
u32 status = 0;
u32 stat;
u8 index;
@@ -134,11 +136,11 @@ u32 boardobjgrp_destruct_super(struct boardobjgrp *pboardobjgrp)
}
/* Destroy the PMU CMD data */
stat = boardobjgrp_pmucmd_destroy_impl(&pboardobjgrp->pmu.set);
stat = boardobjgrp_pmucmd_destroy_impl(g, &pboardobjgrp->pmu.set);
if (status == 0)
status = stat;
stat = boardobjgrp_pmucmd_destroy_impl(&pboardobjgrp->pmu.getstatus);
stat = boardobjgrp_pmucmd_destroy_impl(g, &pboardobjgrp->pmu.getstatus);
if (status == 0)
status = stat;
@@ -163,9 +165,12 @@ u32 boardobjgrp_pmucmd_construct_impl(struct gk20a *g, struct boardobjgrp
return 0;
}
u32 boardobjgrp_pmucmd_destroy_impl(struct boardobjgrp_pmu_cmd *cmd)
u32 boardobjgrp_pmucmd_destroy_impl(struct gk20a *g,
struct boardobjgrp_pmu_cmd *cmd)
{
struct nvgpu_mem *mem = &cmd->surf.sysmem_desc;
nvgpu_pmu_surface_free(g, mem);
return 0;
}

6
drivers/gpu/nvgpu/boardobj/boardobjgrp.h
View File

@@ -153,7 +153,8 @@ typedef u32 boardobjgrp_pmucmd_construct(struct gk20a *g,
/*
* Destroys BOARDOBJGRP PMU SW state. CMD.
*/
typedef u32 boardobjgrp_pmucmd_destroy(struct boardobjgrp_pmu_cmd *cmd);
typedef u32 boardobjgrp_pmucmd_destroy(struct gk20a *g,
struct boardobjgrp_pmu_cmd *cmd);
/*
* init handler for the BOARDOBJGRP PMU CMD. Allocates and maps the
@@ -171,6 +172,7 @@ typedef u32 boardobjgrp_pmucmd_pmuinithandle(struct gk20a *g,
* device group or device-type.
*/
struct boardobjgrp {
struct gk20a *g;
u32 objmask;
bool bconstructed;
u8 type;
@@ -336,7 +338,7 @@ do { \
/* ------------------------ Function Prototypes ----------------------------- */
/* Constructor and destructor */
u32 boardobjgrp_construct_super(struct boardobjgrp *pboardobjgrp);
u32 boardobjgrp_construct_super(struct gk20a *g, struct boardobjgrp *pboardobjgrp);
boardobjgrp_destruct boardobjgrp_destruct_impl;
boardobjgrp_destruct boardobjgrp_destruct_super;

5
drivers/gpu/nvgpu/boardobj/boardobjgrp_e255.c
View File

@@ -27,7 +27,8 @@
#include "boardobjgrp.h"
#include "boardobjgrpmask.h"
u32 boardobjgrpconstruct_e255(struct boardobjgrp_e255 *pboardobjgrp_e255)
u32 boardobjgrpconstruct_e255(struct gk20a *g,
struct boardobjgrp_e255 *pboardobjgrp_e255)
{
u32 status = 0;
u8 objslots;
@@ -44,7 +45,7 @@ u32 boardobjgrpconstruct_e255(struct boardobjgrp_e255 *pboardobjgrp_e255)
pboardobjgrp_e255->super.objslots = objslots;
pboardobjgrp_e255->super.mask = &(pboardobjgrp_e255->mask.super);
status = boardobjgrp_construct_super(&pboardobjgrp_e255->super);
status = boardobjgrp_construct_super(g, &pboardobjgrp_e255->super);
if (status)
goto boardobjgrpconstruct_e255_exit;

2
drivers/gpu/nvgpu/boardobj/boardobjgrp_e255.h
View File

@@ -43,7 +43,7 @@ struct boardobjgrp_e255 {
boardobjgrp_pmudatainit_super(g, pboardpbjgrp, pboardobjgrppmu)
/* Constructor and destructor */
u32 boardobjgrpconstruct_e255(struct boardobjgrp_e255 *pboardobjgrp);
u32 boardobjgrpconstruct_e255(struct gk20a *g, struct boardobjgrp_e255 *pboardobjgrp);
boardobjgrp_destruct boardobjgrpdestruct_e255;
boardobjgrp_pmuhdrdatainit boardobjgrp_pmuhdrdatainit_e255;

5
drivers/gpu/nvgpu/boardobj/boardobjgrp_e32.c
View File

@@ -28,7 +28,8 @@
#include "boardobjgrpmask.h"
u32 boardobjgrpconstruct_e32(struct boardobjgrp_e32 *pboardobjgrp_e32)
u32 boardobjgrpconstruct_e32(struct gk20a *g,
struct boardobjgrp_e32 *pboardobjgrp_e32)
{
u32 status;
u8 objslots;
@@ -45,7 +46,7 @@ u32 boardobjgrpconstruct_e32(struct boardobjgrp_e32 *pboardobjgrp_e32)
pboardobjgrp_e32->super.objslots = objslots;
pboardobjgrp_e32->super.mask = &(pboardobjgrp_e32->mask.super);
status = boardobjgrp_construct_super(&pboardobjgrp_e32->super);
status = boardobjgrp_construct_super(g, &pboardobjgrp_e32->super);
if (status)
goto boardobjgrpconstruct_e32_exit;

2
drivers/gpu/nvgpu/boardobj/boardobjgrp_e32.h
View File

@@ -58,7 +58,7 @@ struct boardobjgrp_e32 {
boardobjgrp_pmudatainit_super(g, pboardpbjgrp, pboardobjgrppmu)
/* Constructor and destructor */
u32 boardobjgrpconstruct_e32(struct boardobjgrp_e32 *pboardobjgrp);
u32 boardobjgrpconstruct_e32(struct gk20a *g, struct boardobjgrp_e32 *pboardobjgrp);
boardobjgrp_destruct boardobjgrpdestruct_e32;
boardobjgrp_pmuhdrdatainit boardobjgrp_pmuhdrdatainit_e32;

2
drivers/gpu/nvgpu/clk/clk_domain.c
View File

@@ -149,7 +149,7 @@ u32 clk_domain_sw_setup(struct gk20a *g)
gk20a_dbg_info("");
status = boardobjgrpconstruct_e32(&g->clk_pmu.clk_domainobjs.super);
status = boardobjgrpconstruct_e32(g, &g->clk_pmu.clk_domainobjs.super);
if (status) {
nvgpu_err(g,
"error creating boardobjgrp for clk domain, status - 0x%x",

2
drivers/gpu/nvgpu/clk/clk_fll.c
View File

@@ -124,7 +124,7 @@ u32 clk_fll_sw_setup(struct gk20a *g)
gk20a_dbg_info("");
status = boardobjgrpconstruct_e32(&g->clk_pmu.avfs_fllobjs.super);
status = boardobjgrpconstruct_e32(g, &g->clk_pmu.avfs_fllobjs.super);
if (status) {
nvgpu_err(g,
"error creating boardobjgrp for fll, status - 0x%x", status);

2
drivers/gpu/nvgpu/clk/clk_freq_controller.c
View File

@@ -398,7 +398,7 @@ u32 clk_freq_controller_sw_setup(struct gk20a *g)
gk20a_dbg_info("");
pclk_freq_controllers = &g->clk_pmu.clk_freq_controllers;
status = boardobjgrpconstruct_e32(&pclk_freq_controllers->super);
status = boardobjgrpconstruct_e32(g, &pclk_freq_controllers->super);
if (status) {
nvgpu_err(g,
"error creating boardobjgrp for clk FCT, status - 0x%x",

2
drivers/gpu/nvgpu/clk/clk_prog.c
View File

@@ -93,7 +93,7 @@ u32 clk_prog_sw_setup(struct gk20a *g)
gk20a_dbg_info("");
status = boardobjgrpconstruct_e255(&g->clk_pmu.clk_progobjs.super);
status = boardobjgrpconstruct_e255(g, &g->clk_pmu.clk_progobjs.super);
if (status) {
nvgpu_err(g,
"error creating boardobjgrp for clk prog, status - 0x%x",

2
drivers/gpu/nvgpu/clk/clk_vf_point.c
View File

@@ -97,7 +97,7 @@ u32 clk_vf_point_sw_setup(struct gk20a *g)
gk20a_dbg_info("");
status = boardobjgrpconstruct_e255(&g->clk_pmu.clk_vf_pointobjs.super);
status = boardobjgrpconstruct_e255(g, &g->clk_pmu.clk_vf_pointobjs.super);
if (status) {
nvgpu_err(g,
"error creating boardobjgrp for clk vfpoint, status - 0x%x",

2
drivers/gpu/nvgpu/clk/clk_vin.c
View File

@@ -257,7 +257,7 @@ u32 clk_vin_sw_setup(struct gk20a *g)
gk20a_dbg_info("");
status = boardobjgrpconstruct_e32(&g->clk_pmu.avfs_vinobjs.super);
status = boardobjgrpconstruct_e32(g, &g->clk_pmu.avfs_vinobjs.super);
if (status) {
nvgpu_err(g,
"error creating boardobjgrp for clk vin, statu - 0x%x",

2
drivers/gpu/nvgpu/perf/vfe_equ.c
View File

@@ -79,7 +79,7 @@ u32 vfe_equ_sw_setup(struct gk20a *g)
gk20a_dbg_info("");
status = boardobjgrpconstruct_e255(&g->perf_pmu.vfe_equobjs.super);
status = boardobjgrpconstruct_e255(g, &g->perf_pmu.vfe_equobjs.super);
if (status) {
nvgpu_err(g,
"error creating boardobjgrp for clk domain, status - 0x%x",

2
drivers/gpu/nvgpu/perf/vfe_var.c
View File

@@ -106,7 +106,7 @@ u32 vfe_var_sw_setup(struct gk20a *g)
gk20a_dbg_info("");
status = boardobjgrpconstruct_e32(&g->perf_pmu.vfe_varobjs.super);
status = boardobjgrpconstruct_e32(g, &g->perf_pmu.vfe_varobjs.super);
if (status) {
nvgpu_err(g,
"error creating boardobjgrp for clk domain, status - 0x%x",

2
drivers/gpu/nvgpu/pmgr/pwrdev.c
View File

@@ -291,7 +291,7 @@ u32 pmgr_device_sw_setup(struct gk20a *g)
struct pwr_devices *ppwrdeviceobjs;
/* Construct the Super Class and override the Interfaces */
status = boardobjgrpconstruct_e32(&g->pmgr_pmu.pmgr_deviceobjs.super);
status = boardobjgrpconstruct_e32(g, &g->pmgr_pmu.pmgr_deviceobjs.super);
if (status) {
nvgpu_err(g,
"error creating boardobjgrp for pmgr devices, status - 0x%x",

6
drivers/gpu/nvgpu/pmgr/pwrmonitor.c
View File

@@ -305,8 +305,8 @@ u32 pmgr_monitor_sw_setup(struct gk20a *g)
u8 indx = 0;
/* Construct the Super Class and override the Interfaces */
status = boardobjgrpconstruct_e32(
&g->pmgr_pmu.pmgr_monitorobjs.pwr_channels);
status = boardobjgrpconstruct_e32(g,
&g->pmgr_pmu.pmgr_monitorobjs.pwr_channels);
if (status) {
nvgpu_err(g,
"error creating boardobjgrp for pmgr channel, status - 0x%x",
@@ -320,7 +320,7 @@ u32 pmgr_monitor_sw_setup(struct gk20a *g)
pboardobjgrp->pmudatainstget = _pwr_channel_pmudata_instget;
/* Construct the Super Class and override the Interfaces */
status = boardobjgrpconstruct_e32(
status = boardobjgrpconstruct_e32(g,
&g->pmgr_pmu.pmgr_monitorobjs.pwr_ch_rels);
if (status) {
nvgpu_err(g,

12
drivers/gpu/nvgpu/pmgr/pwrpolicy.c
View File

@@ -718,8 +718,8 @@ u32 pmgr_policy_sw_setup(struct gk20a *g)
u8 indx = 0;
/* Construct the Super Class and override the Interfaces */
status = boardobjgrpconstruct_e32(
&g->pmgr_pmu.pmgr_policyobjs.pwr_policies);
status = boardobjgrpconstruct_e32(g,
&g->pmgr_pmu.pmgr_policyobjs.pwr_policies);
if (status) {
nvgpu_err(g,
"error creating boardobjgrp for pmgr policy, status - 0x%x",
@@ -727,8 +727,8 @@ u32 pmgr_policy_sw_setup(struct gk20a *g)
goto done;
}
status = boardobjgrpconstruct_e32(
&g->pmgr_pmu.pmgr_policyobjs.pwr_policy_rels);
status = boardobjgrpconstruct_e32(g,
&g->pmgr_pmu.pmgr_policyobjs.pwr_policy_rels);
if (status) {
nvgpu_err(g,
"error creating boardobjgrp for pmgr policy rels, status - 0x%x",
@@ -736,8 +736,8 @@ u32 pmgr_policy_sw_setup(struct gk20a *g)
goto done;
}
status = boardobjgrpconstruct_e32(
&g->pmgr_pmu.pmgr_policyobjs.pwr_violations);
status = boardobjgrpconstruct_e32(g,
&g->pmgr_pmu.pmgr_policyobjs.pwr_violations);
if (status) {
nvgpu_err(g,
"error creating boardobjgrp for pmgr violations, status - 0x%x",

2
drivers/gpu/nvgpu/pstate/pstate.c
View File

@@ -363,7 +363,7 @@ static int pstate_sw_setup(struct gk20a *g)
if (err)
return err;
err = boardobjgrpconstruct_e32(&g->perf_pmu.pstatesobjs.super);
err = boardobjgrpconstruct_e32(g, &g->perf_pmu.pstatesobjs.super);
if (err) {
nvgpu_err(g,
"error creating boardobjgrp for pstates, err=%d",

3
drivers/gpu/nvgpu/therm/thrmchannel.c
View File

@@ -217,7 +217,8 @@ u32 therm_channel_sw_setup(struct gk20a *g)
struct therm_channels *pthermchannelobjs;
/* Construct the Super Class and override the Interfaces */
status = boardobjgrpconstruct_e32(&g->therm_pmu.therm_channelobjs.super);
status = boardobjgrpconstruct_e32(g,
&g->therm_pmu.therm_channelobjs.super);
if (status) {
nvgpu_err(g,
"error creating boardobjgrp for therm devices, status - 0x%x",

3
drivers/gpu/nvgpu/therm/thrmdev.c
View File

@@ -164,7 +164,8 @@ u32 therm_device_sw_setup(struct gk20a *g)
struct therm_devices *pthermdeviceobjs;
/* Construct the Super Class and override the Interfaces */
status = boardobjgrpconstruct_e32(&g->therm_pmu.therm_deviceobjs.super);
status = boardobjgrpconstruct_e32(g,
&g->therm_pmu.therm_deviceobjs.super);
if (status) {
nvgpu_err(g,
"error creating boardobjgrp for therm devices, status - 0x%x",

4
drivers/gpu/nvgpu/volt/volt_dev.c
View File

@@ -527,8 +527,8 @@ u32 volt_dev_sw_setup(struct gk20a *g)
gk20a_dbg_info("");
status = boardobjgrpconstruct_e32(&g->perf_pmu.volt.volt_dev_metadata.
volt_devices);
status = boardobjgrpconstruct_e32(g,
&g->perf_pmu.volt.volt_dev_metadata.volt_devices);
if (status) {
nvgpu_err(g,
"error creating boardobjgrp for volt rail, status - 0x%x",

2
drivers/gpu/nvgpu/volt/volt_policy.c
View File

@@ -312,7 +312,7 @@ u32 volt_policy_sw_setup(struct gk20a *g)
gk20a_dbg_info("");
status = boardobjgrpconstruct_e32(
status = boardobjgrpconstruct_e32(g,
&g->perf_pmu.volt.volt_policy_metadata.volt_policies);
if (status) {
nvgpu_err(g,

4
drivers/gpu/nvgpu/volt/volt_rail.c
View File

@@ -375,8 +375,8 @@ u32 volt_rail_sw_setup(struct gk20a *g)
gk20a_dbg_info("");
status = boardobjgrpconstruct_e32(&g->perf_pmu.volt.volt_rail_metadata.
volt_rails);
status = boardobjgrpconstruct_e32(g,
&g->perf_pmu.volt.volt_rail_metadata.volt_rails);
if (status) {
nvgpu_err(g,
"error creating boardobjgrp for volt rail, status - 0x%x",