gpu: nvgpu: Add api to query the availability of multi GR support

* Added a new api(nvgpu_gr_is_multi_gr_enabled()) to query the
  availability of multi GR support when MIG is enabled.

JIRA NVGPU-5650

Change-Id: I3f8c29db966afb8d72021a093e009492f134ec9d
Signed-off-by: Lakshmanan M <lm@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2488399
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Dinesh T <dt@nvidia.com>
Reviewed-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
This commit is contained in:
Lakshmanan M
2021-02-23 22:14:53 +05:30
committed by mobile promotions
parent 06f554318a
commit 1438689a89
3 changed files with 22 additions and 14 deletions

View File

@@ -1,7 +1,7 @@
/*
* GR MANAGER
*
* Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2020-2021, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -170,7 +170,7 @@ int nvgpu_grmgr_config_gr_remap_window(struct gk20a *g,
{
int err = 0;
#if defined(CONFIG_NVGPU_NEXT) && defined(CONFIG_NVGPU_MIG)
if (nvgpu_is_enabled(g, NVGPU_SUPPORT_MIG)) {
if (nvgpu_grmgr_is_multi_gr_enabled(g)) {
/*
* GR remap window enable/disable sequence for a GR
* SYSPIPE PGRAPH programming:
@@ -301,7 +301,7 @@ static inline u32 nvgpu_grmgr_get_gpu_instance_id(struct gk20a *g,
{
u32 gpu_instance_id = 0U;
if (nvgpu_is_enabled(g, NVGPU_SUPPORT_MIG)) {
if (nvgpu_grmgr_is_multi_gr_enabled(g)) {
/* 0th entry is physical device gpu instance */
gpu_instance_id = nvgpu_safe_add_u32(gr_instance_id, 1U);
@@ -366,7 +366,7 @@ u32 nvgpu_grmgr_get_gr_instance_id(struct gk20a *g, u32 gpu_instance_id)
u32 gr_instance_id = 0U;
/* TODO : Add gr_instance_id for physical device when MIG is enabled. */
if ((nvgpu_is_enabled(g, NVGPU_SUPPORT_MIG)) &&
if ((nvgpu_grmgr_is_multi_gr_enabled(g)) &&
(gpu_instance_id != 0U)) {
if (gpu_instance_id < g->mig.num_gpu_instances) {
/* 0th entry is physical device gpu instance */
@@ -446,7 +446,7 @@ u32 nvgpu_grmgr_get_gpu_instance_runlist_id(struct gk20a *g,
u32 nvgpu_grmgr_get_gr_instance_id_for_syspipe(struct gk20a *g,
u32 gr_syspipe_id)
{
if (nvgpu_is_enabled(g, NVGPU_SUPPORT_MIG)) {
if (nvgpu_grmgr_is_multi_gr_enabled(g)) {
u32 gr_instance_id = 0U;
u32 index;
/* 0th entry is physical device gpu instance. */

View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2020-2021, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -32,7 +32,7 @@
#define nvgpu_gr_get_cur_instance_id(g) \
({ \
u32 current_gr_instance_id = 0U; \
if (nvgpu_is_enabled(g, NVGPU_SUPPORT_MIG)) { \
if (nvgpu_grmgr_is_multi_gr_enabled(g)) { \
if (nvgpu_mutex_tryacquire(&g->mig.gr_syspipe_lock) == 0) { \
current_gr_instance_id = g->mig.cur_gr_instance; \
} else { \
@@ -54,7 +54,7 @@
#ifdef CONFIG_NVGPU_MIG
#define nvgpu_gr_exec_for_each_instance(g, func) \
({ \
if (nvgpu_is_enabled(g, NVGPU_SUPPORT_MIG)) { \
if (nvgpu_grmgr_is_multi_gr_enabled(g)) { \
u32 gr_instance_id = 0U; \
for (; gr_instance_id < g->num_gr_instances; gr_instance_id++) { \
u32 gr_syspipe_id = nvgpu_gr_get_syspipe_id(g, gr_instance_id); \
@@ -75,7 +75,7 @@
#define nvgpu_gr_exec_with_ret_for_each_instance(g, func) \
({ \
int err = 0; \
if (nvgpu_is_enabled(g, NVGPU_SUPPORT_MIG)) { \
if (nvgpu_grmgr_is_multi_gr_enabled(g)) { \
u32 gr_instance_id = 0U; \
for (; gr_instance_id < g->num_gr_instances; gr_instance_id++) { \
u32 gr_syspipe_id = nvgpu_gr_get_syspipe_id(g, gr_instance_id); \
@@ -99,7 +99,7 @@
#ifdef CONFIG_NVGPU_MIG
#define nvgpu_gr_exec_for_all_instances(g, func) \
({ \
if (nvgpu_is_enabled(g, NVGPU_SUPPORT_MIG)) { \
if (nvgpu_grmgr_is_multi_gr_enabled(g)) { \
nvgpu_grmgr_config_gr_remap_window(g, NVGPU_MIG_INVALID_GR_SYSPIPE_ID, false); \
g->mig.cur_gr_instance = 0; \
(func); \
@@ -115,7 +115,7 @@
#ifdef CONFIG_NVGPU_MIG
#define nvgpu_gr_exec_for_instance(g, gr_instance_id, func) \
({ \
if (nvgpu_is_enabled(g, NVGPU_SUPPORT_MIG)) { \
if (nvgpu_grmgr_is_multi_gr_enabled(g)) { \
u32 gr_syspipe_id = nvgpu_gr_get_syspipe_id(g, \
gr_instance_id); \
nvgpu_grmgr_config_gr_remap_window(g, gr_syspipe_id, \
@@ -136,7 +136,7 @@
#define nvgpu_gr_exec_with_ret_for_instance(g, gr_instance_id, func, type) \
({ \
typeof(type) ret; \
if (nvgpu_is_enabled(g, NVGPU_SUPPORT_MIG)) { \
if (nvgpu_grmgr_is_multi_gr_enabled(g)) { \
u32 gr_syspipe_id = nvgpu_gr_get_syspipe_id(g, gr_instance_id); \
nvgpu_grmgr_config_gr_remap_window(g, gr_syspipe_id, true); \
g->mig.cur_gr_instance = gr_instance_id; \
@@ -168,7 +168,7 @@
#define nvgpu_gr_get_gpu_instance_config_ptr(g, gpu_instance_id) \
({ \
struct nvgpu_gr_config *gr_config = NULL; \
if (nvgpu_is_enabled(g, NVGPU_SUPPORT_MIG)) { \
if (nvgpu_grmgr_is_multi_gr_enabled(g)) { \
u32 gr_instance_id = nvgpu_grmgr_get_gr_instance_id(g, \
gpu_instance_id); \
if (gr_instance_id < g->num_gr_instances) { \

View File

@@ -1,7 +1,7 @@
/*
* GR MANAGER
*
* Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2020-2021, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -27,6 +27,8 @@
#include <nvgpu/types.h>
#include <nvgpu/mig.h>
#include <nvgpu/enabled.h>
#include <nvgpu/gk20a.h>
struct gk20a;
@@ -57,4 +59,10 @@ static inline bool nvgpu_grmgr_is_mig_type_gpu_instance(
return (gpu_instance->gpu_instance_type == NVGPU_MIG_TYPE_MIG);
}
static inline bool nvgpu_grmgr_is_multi_gr_enabled(struct gk20a *g)
{
return ((nvgpu_is_enabled(g, NVGPU_SUPPORT_MIG)) &&
(g->mig.num_gpu_instances > 1U));
}
#endif /* NVGPU_GRMGR_H */