nv-tegra-mirror/linux-nvgpu
1
0
Fork 0
mirror of git://nv-tegra.nvidia.com/linux-nvgpu.git synced 2025-12-25 11:04:51 +03:00
Code Issues Packages Projects Releases Wiki Activity

gpu: nvgpu: move & rename acr_gm20b to acr_desc

Browse Source 
acr_gm20b renamed to acr_desc to support
multiple gpu chips

JIRA DNVGPU-10

Change-Id: Ib3b38d5845043f026ddc365a682b7bb454463326
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1152401
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
This commit is contained in:
Mahantesh Kumbar
2016-05-24 14:32:09 +05:30
committed by Terje Bergstrom
parent e9d5e7dfca
commit 147330c2da
4 changed files with 44 additions and 23 deletions
Download Patch File Download Diff File Expand all files Collapse all files

38
drivers/gpu/nvgpu/acr.h Normal file
View File

@@ -0,0 +1,38 @@
/*
* Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#ifndef __ACR_H_
#define __ACR_H_
#include "gm20b/mm_gm20b.h"
#include "gm20b/acr_gm20b.h"
struct acr_desc {
struct mem_desc ucode_blob;
struct bin_hdr *bl_bin_hdr;
struct hsflcn_bl_desc *pmu_hsbl_desc;
struct bin_hdr *hsbin_hdr;
struct acr_fw_header *fw_hdr;
u32 pmu_args;
const struct firmware *acr_fw;
struct flcn_acr_desc *acr_dmem_desc;
struct mem_desc acr_ucode;
const struct firmware *hsbl_fw;
struct mem_desc hsbl_ucode;
struct flcn_bl_dmem_desc bl_dmem_desc;
const struct firmware *pmu_fw;
const struct firmware *pmu_desc;
u32 capabilities;
};
#endif /*__ACR_H_*/

5
drivers/gpu/nvgpu/gk20a/gk20a.h
View File

@@ -26,7 +26,7 @@ struct sim_gk20a;
struct gk20a_ctxsw_ucode_segments;
struct gk20a_fecs_trace;
struct gk20a_ctxsw_trace;
struct acr_gm20b;
struct acr_desc;
#include <linux/sched.h>
#include <linux/spinlock.h>
@@ -49,6 +49,7 @@ struct acr_gm20b;
#include "therm_gk20a.h"
#include "platform_gk20a.h"
#include "gm20b/acr_gm20b.h"
#include "acr.h"
#include "cde_gk20a.h"
#include "debug_gk20a.h"
@@ -669,7 +670,7 @@ struct gk20a {
struct sim_gk20a sim;
struct mm_gk20a mm;
struct pmu_gk20a pmu;
struct acr_gm20b acr;
struct acr_desc acr;
struct cooling_device_gk20a gk20a_cdev;
/* Save pmu fw here so that it lives cross suspend/resume.

6
drivers/gpu/nvgpu/gm20b/acr_gm20b.c
View File

@@ -1058,7 +1058,7 @@ int gm20b_bootstrap_hs_flcn(struct gk20a *g)
u32 img_size_in_bytes = 0;
u32 status, size;
u64 start;
struct acr_gm20b *acr = &g->acr;
struct acr_desc *acr = &g->acr;
const struct firmware *acr_fw = acr->acr_fw;
struct flcn_bl_dmem_desc *bl_dmem_desc = &acr->bl_dmem_desc;
u32 *acr_ucode_header_t210_load;
@@ -1204,7 +1204,7 @@ static int bl_bootstrap(struct pmu_gk20a *pmu,
struct flcn_bl_dmem_desc *pbl_desc, u32 bl_sz)
{
struct gk20a *g = gk20a_from_pmu(pmu);
struct acr_gm20b *acr = &g->acr;
struct acr_desc *acr = &g->acr;
struct mm_gk20a *mm = &g->mm;
u32 imem_dst_blk = 0;
u32 virt_addr = 0;
@@ -1375,7 +1375,7 @@ int pmu_exec_gen_bl(struct gk20a *g, void *desc, u8 b_wait_for_halt)
struct device *d = dev_from_gk20a(g);
int err = 0;
u32 bl_sz;
struct acr_gm20b *acr = &g->acr;
struct acr_desc *acr = &g->acr;
const struct firmware *hsbl_fw = acr->hsbl_fw;
struct hsflcn_bl_desc *pmu_bl_gm10x_desc;
u32 *pmu_bl_gm10x = NULL;

18
drivers/gpu/nvgpu/gm20b/acr_gm20b.h
View File

@@ -386,24 +386,6 @@ struct acr_fw_header {
u32 hdr_size; /*size of above header*/
};
struct acr_gm20b {
struct mem_desc ucode_blob;
struct bin_hdr *bl_bin_hdr;
struct hsflcn_bl_desc *pmu_hsbl_desc;
struct bin_hdr *hsbin_hdr;
struct acr_fw_header *fw_hdr;
u32 pmu_args;
const struct firmware *acr_fw;
struct flcn_acr_desc *acr_dmem_desc;
struct mem_desc acr_ucode;
const struct firmware *hsbl_fw;
struct mem_desc hsbl_ucode;
struct flcn_bl_dmem_desc bl_dmem_desc;
const struct firmware *pmu_fw;
const struct firmware *pmu_desc;
u32 capabilities;
};
void gm20b_init_secure_pmu(struct gpu_ops *gops);
int prepare_ucode_blob(struct gk20a *g);
int gm20b_pmu_setup_sw(struct gk20a *g);