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gpu: nvgpu: Refactor Clk, Volt sub-unit

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As a part of refactoring, we need to move the volt unit from perf to pmu
as it belongs there and also move the arbitor specific functions under
CLK_ARB as they will be removed from safety build.
This patch does the following
*Move volt struct from perf to pmu
*Move volt setup from pmu_pstate to volt
*Move clk freq related functions into CLK_ARB

NVGPU-4491
NVGPU-4492

Change-Id: I7180cd12bbf91cc4d2e79b6e2d71c16e494c8ff0
Signed-off-by: Abdul Salam <absalam@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2268215
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Abdul Salam
2019-12-27 18:43:26 +05:30
committed by Alex Waterman
parent 933b62a36e
commit 14b218c284
18 changed files with 176 additions and 105 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
drivers/gpu/nvgpu/Makefile
View File

@@ -156,6 +156,7 @@ nvgpu-y += \
common/pmu/pmgr/pmgrpmu.o \
common/pmu/pmgr/pwrmonitor.o \
common/pmu/pmgr/pwrpolicy.o \
common/pmu/volt/volt.o \
common/pmu/volt/volt_rail.o \
common/pmu/volt/volt_dev.o \
common/pmu/volt/volt_policy.o \

1
drivers/gpu/nvgpu/Makefile.sources
View File

@@ -433,6 +433,7 @@ srcs += \
common/pmu/boardobj/boardobjgrp_e255.c \
common/pmu/boardobj/boardobjgrp_e32.c \
common/pmu/clk/clk.c \
common/pmu/volt/volt.c \
common/pmu/clk/clk_domain.c \
common/pmu/clk/clk_fll.c \
common/pmu/clk/clk_prog.c \

1
drivers/gpu/nvgpu/common/pmu/perf/vfe_equ.c
View File

@@ -30,6 +30,7 @@
#include <nvgpu/pmu/pmuif/ctrlclk.h>
#include <nvgpu/pmu/pmuif/ctrlvolt.h>
#include <nvgpu/pmu/perf.h>
#include <nvgpu/pmu/volt.h>
#include <nvgpu/pmu/clk/clk.h>
#include <nvgpu/pmu/clk/clk_fll.h>
#include <nvgpu/pmu/cmd.h>

67
drivers/gpu/nvgpu/common/pmu/pmu_pstate.c
View File

@@ -51,6 +51,10 @@ void nvgpu_pmu_pstate_deinit(struct gk20a *g)
nvgpu_perf_pmu_free_pmupstate(g);
}
if (g->pmu->volt != NULL) {
nvgpu_pmu_volt_deinit(g);
}
if (g->pmu->clk_pmu != NULL) {
nvgpu_clk_domain_free_pmupstate(g);
nvgpu_clk_prog_free_pmupstate(g);
@@ -131,6 +135,11 @@ static int pmu_pstate_init(struct gk20a *g)
return err;
}
err = nvgpu_pmu_volt_init(g);
if (err != 0) {
return err;
}
err = pmgr_pmu_init_pmupstate(g);
if (err != 0) {
pmgr_pmu_free_pmupstate(g);
@@ -140,29 +149,6 @@ static int pmu_pstate_init(struct gk20a *g)
return 0;
}
static int pmu_pstate_volt_sw_setup(struct gk20a *g)
{
int err;
nvgpu_log_fn(g, " ");
err = nvgpu_volt_rail_sw_setup(g);
if (err != 0) {
return err;
}
err = nvgpu_volt_dev_sw_setup(g);
if (err != 0) {
return err;
}
err = nvgpu_volt_policy_sw_setup(g);
if (err != 0) {
return err;
}
return 0;
}
static int pmu_pstate_clk_sw_setup(struct gk20a *g)
{
int err;
@@ -254,7 +240,7 @@ int nvgpu_pmu_pstate_sw_setup(struct gk20a *g)
return err;
}
err = pmu_pstate_volt_sw_setup(g);
err = nvgpu_pmu_volt_sw_setup(g);
if (err != 0) {
nvgpu_err(g, "Volt sw setup failed");
return err;
@@ -303,37 +289,6 @@ err_perf_pmu_init_pmupstate:
return err;
}
static int pmu_pstate_volt_pmu_setup(struct gk20a *g)
{
int err;
nvgpu_log_fn(g, " ");
err = nvgpu_volt_rail_pmu_setup(g);
if (err != 0) {
return err;
}
err = nvgpu_volt_dev_pmu_setup(g);
if (err != 0) {
return err;
}
err = nvgpu_volt_policy_pmu_setup(g);
if (err != 0) {
return err;
}
err = nvgpu_volt_send_load_cmd_to_pmu(g);
if (err != 0) {
nvgpu_err(g,
"Failed to send VOLT LOAD CMD to PMU: status = 0x%08x.",
err);
return err;
}
return 0;
}
static int pmu_pstate_clk_pmu_setup(struct gk20a *g)
{
int err;
@@ -426,7 +381,7 @@ int nvgpu_pmu_pstate_pmu_setup(struct gk20a *g)
}
}
err = pmu_pstate_volt_pmu_setup(g);
err = nvgpu_pmu_volt_pmu_setup(g);
if (err != 0) {
nvgpu_err(g, "Failed to send VOLT pmu setup");
return err;

112
drivers/gpu/nvgpu/common/pmu/volt/volt.c Normal file
View File

@@ -0,0 +1,112 @@
/*
* Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#include <nvgpu/pmu/volt.h>
#include <nvgpu/gk20a.h>
#include "volt_rail.h"
#include "volt_dev.h"
#include "volt_policy.h"
#include "volt_pmu.h"
int nvgpu_pmu_volt_sw_setup(struct gk20a *g)
{
int err;
nvgpu_log_fn(g, " ");
err = nvgpu_volt_rail_sw_setup(g);
if (err != 0) {
return err;
}
err = nvgpu_volt_dev_sw_setup(g);
if (err != 0) {
return err;
}
err = nvgpu_volt_policy_sw_setup(g);
if (err != 0) {
return err;
}
return 0;
}
int nvgpu_pmu_volt_init(struct gk20a *g)
{
int err = 0;
nvgpu_log_fn(g, " ");
/* If already allocated, do not re-allocate */
if (g->pmu->volt != NULL) {
return 0;
}
g->pmu->volt = (struct nvgpu_pmu_volt *) nvgpu_kzalloc(g,
sizeof(struct nvgpu_pmu_volt));
if (g->pmu->volt == NULL) {
err = -ENOMEM;
return err;
}
return err;
}
void nvgpu_pmu_volt_deinit(struct gk20a *g)
{
if ((g->pmu != NULL) && (g->pmu->volt != NULL)) {
nvgpu_kfree(g, g->pmu->volt);
g->pmu->volt = NULL;
}
}
int nvgpu_pmu_volt_pmu_setup(struct gk20a *g)
{
int err;
nvgpu_log_fn(g, " ");
err = nvgpu_volt_rail_pmu_setup(g);
if (err != 0) {
return err;
}
err = nvgpu_volt_dev_pmu_setup(g);
if (err != 0) {
return err;
}
err = nvgpu_volt_policy_pmu_setup(g);
if (err != 0) {
return err;
}
err = nvgpu_volt_send_load_cmd_to_pmu(g);
if (err != 0) {
nvgpu_err(g,
"Failed to send VOLT LOAD CMD to PMU: status = 0x%08x.",
err);
return err;
}
return 0;
}

14
drivers/gpu/nvgpu/common/pmu/volt/volt_dev.c
View File

@@ -445,7 +445,7 @@ static int volt_device_state_init(struct gk20a *g,
/* Build VOLT_RAIL SW state from VOLT_DEVICE SW state. */
/* If VOLT_RAIL isn't supported, exit. */
if (VOLT_RAIL_VOLT_3X_SUPPORTED(&g->perf_pmu->volt)) {
if (VOLT_RAIL_VOLT_3X_SUPPORTED(g->pmu->volt)) {
rail_idx = nvgpu_volt_rail_volt_domain_convert_to_idx(g,
pvolt_dev->volt_domain);
if (rail_idx == CTRL_BOARDOBJ_IDX_INVALID) {
@@ -455,7 +455,7 @@ static int volt_device_state_init(struct gk20a *g,
goto done;
}
pRail = VOLT_GET_VOLT_RAIL(&g->perf_pmu->volt, rail_idx);
pRail = VOLT_GET_VOLT_RAIL(g->pmu->volt, rail_idx);
if (pRail == NULL) {
nvgpu_err(g,
"could not obtain ptr to rail object from rail index");
@@ -487,7 +487,7 @@ int nvgpu_volt_dev_pmu_setup(struct gk20a *g)
nvgpu_log_info(g, " ");
pboardobjgrp = &g->perf_pmu->volt.volt_dev_metadata.volt_devices.super;
pboardobjgrp = &g->pmu->volt->volt_dev_metadata.volt_devices.super;
if (!pboardobjgrp->bconstructed) {
return -EINVAL;
@@ -509,7 +509,7 @@ int nvgpu_volt_dev_sw_setup(struct gk20a *g)
nvgpu_log_info(g, " ");
status = nvgpu_boardobjgrp_construct_e32(g,
&g->perf_pmu->volt.volt_dev_metadata.volt_devices);
&g->pmu->volt->volt_dev_metadata.volt_devices);
if (status != 0) {
nvgpu_err(g,
"error creating boardobjgrp for volt rail, "
@@ -517,12 +517,12 @@ int nvgpu_volt_dev_sw_setup(struct gk20a *g)
goto done;
}
pboardobjgrp = &g->perf_pmu->volt.volt_dev_metadata.volt_devices.super;
pboardobjgrp = &g->pmu->volt->volt_dev_metadata.volt_devices.super;
pboardobjgrp->pmudatainstget = _volt_device_devgrp_pmudata_instget;
/* Obtain Voltage Rail Table from VBIOS */
status = volt_get_volt_devices_table(g, &g->perf_pmu->volt.
status = volt_get_volt_devices_table(g, &g->pmu->volt->
volt_dev_metadata);
if (status != 0) {
goto done;
@@ -541,7 +541,7 @@ int nvgpu_volt_dev_sw_setup(struct gk20a *g)
}
/* update calibration to fuse */
BOARDOBJGRP_FOR_EACH(&(g->perf_pmu->volt.volt_dev_metadata.volt_devices.
BOARDOBJGRP_FOR_EACH(&(g->pmu->volt->volt_dev_metadata.volt_devices.
super),
struct voltage_device *, pvolt_device, i) {
status = volt_device_state_init(g, pvolt_device);

3
drivers/gpu/nvgpu/common/pmu/volt/volt_dev.h
View File

@@ -70,4 +70,7 @@ struct voltage_device_pwm_entry {
};
/* PWM end */
int nvgpu_volt_dev_sw_setup(struct gk20a *g);
int nvgpu_volt_dev_pmu_setup(struct gk20a *g);
#endif /* NVGPU_VOLT_DEV_H */

2
drivers/gpu/nvgpu/common/pmu/volt/volt_pmu.h
View File

@@ -23,6 +23,6 @@
#ifndef NVGPU_VOLT_PMU_H
#define NVGPU_VOLT_PMU_H
u32 volt_pmu_send_load_cmd_to_pmu(struct gk20a *g);
int nvgpu_volt_send_load_cmd_to_pmu(struct gk20a *g);
#endif /* NVGPU_VOLT_PMU_H */

11
drivers/gpu/nvgpu/common/pmu/volt/volt_policy.c
View File

@@ -28,6 +28,7 @@
#include <nvgpu/string.h>
#include <nvgpu/pmu/pmuif/ctrlvolt.h>
#include <nvgpu/pmu/perf.h>
#include <nvgpu/pmu/volt.h>
#include "volt_policy.h"
@@ -332,7 +333,7 @@ static int _volt_policy_grp_pmudatainit_super(struct gk20a *g,
struct nv_pmu_volt_volt_policy_boardobjgrp_set_header *pset =
(struct nv_pmu_volt_volt_policy_boardobjgrp_set_header *)
pboardobjgrppmu;
struct obj_volt *volt = (struct obj_volt *)pboardobjgrp;
struct nvgpu_pmu_volt *volt = (struct nvgpu_pmu_volt *)pboardobjgrp;
int status = 0;
status = boardobjgrp_pmudatainit_e32(g, pboardobjgrp, pboardobjgrppmu);
@@ -357,7 +358,7 @@ int nvgpu_volt_policy_pmu_setup(struct gk20a *g)
nvgpu_log_info(g, " ");
pboardobjgrp =
&g->perf_pmu->volt.volt_policy_metadata.volt_policies.super;
&g->pmu->volt->volt_policy_metadata.volt_policies.super;
if (!pboardobjgrp->bconstructed) {
return -EINVAL;
@@ -377,7 +378,7 @@ int nvgpu_volt_policy_sw_setup(struct gk20a *g)
nvgpu_log_info(g, " ");
status = nvgpu_boardobjgrp_construct_e32(g,
&g->perf_pmu->volt.volt_policy_metadata.volt_policies);
&g->pmu->volt->volt_policy_metadata.volt_policies);
if (status != 0) {
nvgpu_err(g,
"error creating boardobjgrp for volt rail, "
@@ -386,13 +387,13 @@ int nvgpu_volt_policy_sw_setup(struct gk20a *g)
}
pboardobjgrp =
&g->perf_pmu->volt.volt_policy_metadata.volt_policies.super;
&g->pmu->volt->volt_policy_metadata.volt_policies.super;
pboardobjgrp->pmudatainstget = _volt_policy_devgrp_pmudata_instget;
pboardobjgrp->pmudatainit = _volt_policy_grp_pmudatainit_super;
/* Obtain Voltage Rail Table from VBIOS */
status = volt_get_volt_policy_table(g, &g->perf_pmu->volt.
status = volt_get_volt_policy_table(g, &g->pmu->volt->
volt_policy_metadata);
if (status != 0) {
goto done;

3
drivers/gpu/nvgpu/common/pmu/volt/volt_policy.h
View File

@@ -47,4 +47,7 @@ struct voltage_policy_single_rail_multi_step {
u32 ramp_down_step_size_uv;
};
int nvgpu_volt_policy_sw_setup(struct gk20a *g);
int nvgpu_volt_policy_pmu_setup(struct gk20a *g);
#endif /* NVGPU_VOLT_POLICY_H */

33
drivers/gpu/nvgpu/common/pmu/volt/volt_rail.c
View File

@@ -44,7 +44,7 @@ static int volt_rail_state_init(struct gk20a *g,
for (i = 0; i < CTRL_VOLT_RAIL_VOLT_DELTA_MAX_ENTRIES; i++) {
pvolt_rail->volt_delta_uv[i] = (int)NV_PMU_VOLT_VALUE_0V_IN_UV;
g->perf_pmu->volt.volt_rail_metadata.ext_rel_delta_uv[i] =
g->pmu->volt->volt_rail_metadata.ext_rel_delta_uv[i] =
NV_PMU_VOLT_VALUE_0V_IN_UV;
}
@@ -100,7 +100,7 @@ static int volt_rail_init_pmudata_super(struct gk20a *g,
for (i = 0; i < CTRL_VOLT_RAIL_VOLT_DELTA_MAX_ENTRIES; i++) {
rail_pmu_data->volt_delta_uv[i] = prail->volt_delta_uv[i] +
(int)g->perf_pmu->volt.volt_rail_metadata.ext_rel_delta_uv[i];
(int)g->pmu->volt->volt_rail_metadata.ext_rel_delta_uv[i];
}
status = nvgpu_boardobjgrpmask_export(&prail->volt_dev_mask.super,
@@ -347,8 +347,8 @@ static int nvgpu_volt_rail_boardobj_grp_get_status(struct gk20a *g)
nvgpu_log_info(g, " ");
pboardobjgrp = &g->perf_pmu->volt.volt_rail_metadata.volt_rails.super;
pboardobjgrpmask = &g->perf_pmu->volt.volt_rail_metadata.volt_rails.mask.super;
pboardobjgrp = &g->pmu->volt->volt_rail_metadata.volt_rails.super;
pboardobjgrpmask = &g->pmu->volt->volt_rail_metadata.volt_rails.mask.super;
status = pboardobjgrp->pmugetstatus(g, pboardobjgrp, pboardobjgrpmask);
if (status != 0) {
nvgpu_err(g, "err getting boardobjs from pmu");
@@ -384,7 +384,7 @@ int nvgpu_volt_rail_sw_setup(struct gk20a *g)
nvgpu_log_info(g, " ");
status = nvgpu_boardobjgrp_construct_e32(g,
&g->perf_pmu->volt.volt_rail_metadata.volt_rails);
&g->pmu->volt->volt_rail_metadata.volt_rails);
if (status != 0) {
nvgpu_err(g,
"error creating boardobjgrp for volt rail, "
@@ -392,17 +392,16 @@ int nvgpu_volt_rail_sw_setup(struct gk20a *g)
goto done;
}
pboardobjgrp = &g->perf_pmu->volt.volt_rail_metadata.volt_rails.super;
pboardobjgrp = &g->pmu->volt->volt_rail_metadata.volt_rails.super;
pboardobjgrp->pmudatainstget = _volt_rail_devgrp_pmudata_instget;
pboardobjgrp->pmustatusinstget = _volt_rail_devgrp_pmustatus_instget;
g->perf_pmu->volt.volt_rail_metadata.pct_delta =
g->pmu->volt->volt_rail_metadata.pct_delta =
NV_PMU_VOLT_VALUE_0V_IN_UV;
/* Obtain Voltage Rail Table from VBIOS */
status = volt_get_volt_rail_table(g, &g->perf_pmu->volt.
volt_rail_metadata);
status = volt_get_volt_rail_table(g, &g->pmu->volt->volt_rail_metadata);
if (status != 0) {
goto done;
}
@@ -420,7 +419,7 @@ int nvgpu_volt_rail_sw_setup(struct gk20a *g)
}
status = BOARDOBJGRP_PMU_CMD_GRP_GET_STATUS_CONSTRUCT(g,
&g->perf_pmu->volt.volt_rail_metadata.volt_rails.super,
&g->pmu->volt->volt_rail_metadata.volt_rails.super,
volt, VOLT, volt_rail, VOLT_RAIL);
if (status != 0) {
nvgpu_err(g,
@@ -430,7 +429,7 @@ int nvgpu_volt_rail_sw_setup(struct gk20a *g)
}
/* update calibration to fuse */
BOARDOBJGRP_FOR_EACH(&(g->perf_pmu->volt.volt_rail_metadata.
BOARDOBJGRP_FOR_EACH(&(g->pmu->volt->volt_rail_metadata.
volt_rails.super),
struct voltage_rail *, pvolt_rail, i) {
status = volt_rail_state_init(g, pvolt_rail);
@@ -454,7 +453,7 @@ int nvgpu_volt_rail_pmu_setup(struct gk20a *g)
nvgpu_log_info(g, " ");
pboardobjgrp = &g->perf_pmu->volt.volt_rail_metadata.volt_rails.super;
pboardobjgrp = &g->pmu->volt->volt_rail_metadata.volt_rails.super;
if (!pboardobjgrp->bconstructed) {
return -EINVAL;
@@ -469,7 +468,7 @@ int nvgpu_volt_rail_pmu_setup(struct gk20a *g)
u8 nvgpu_volt_rail_vbios_volt_domain_convert_to_internal(struct gk20a *g,
u8 vbios_volt_domain)
{
if (g->perf_pmu->volt.volt_rail_metadata.volt_domain_hal ==
if (g->pmu->volt->volt_rail_metadata.volt_domain_hal ==
CTRL_VOLT_DOMAIN_HAL_GP10X_SINGLE_RAIL) {
return CTRL_VOLT_DOMAIN_LOGIC;
} else {
@@ -480,7 +479,7 @@ u8 nvgpu_volt_rail_vbios_volt_domain_convert_to_internal(struct gk20a *g,
u8 nvgpu_volt_rail_volt_domain_convert_to_idx(struct gk20a *g, u8 volt_domain)
{
if (g->perf_pmu->volt.volt_rail_metadata.volt_domain_hal ==
if (g->pmu->volt->volt_rail_metadata.volt_domain_hal ==
CTRL_VOLT_DOMAIN_HAL_GP10X_SINGLE_RAIL) {
return 0U;
} else {
@@ -547,7 +546,7 @@ int nvgpu_volt_get_vmin_vmax_ps35(struct gk20a *g, u32 *vmin_uv, u32 *vmax_uv)
return status;
}
pboardobjgrp = &g->perf_pmu->volt.volt_rail_metadata.volt_rails.super;
pboardobjgrp = &g->pmu->volt->volt_rail_metadata.volt_rails.super;
BOARDOBJGRP_FOR_EACH(pboardobjgrp, struct boardobj*, pboardobj, index) {
volt_rail = (struct voltage_rail *)(void *)pboardobj;
@@ -576,7 +575,7 @@ int nvgpu_volt_get_curr_volt_ps35(struct gk20a *g, u32 *vcurr_uv)
return status;
}
pboardobjgrp = &g->perf_pmu->volt.volt_rail_metadata.volt_rails.super;
pboardobjgrp = &g->pmu->volt->volt_rail_metadata.volt_rails.super;
BOARDOBJGRP_FOR_EACH(pboardobjgrp, struct boardobj*, pboardobj, index) {
volt_rail = (struct voltage_rail *)(void *)pboardobj;
@@ -595,7 +594,7 @@ u8 nvgpu_volt_get_vmargin_ps35(struct gk20a *g)
struct voltage_rail *volt_rail = NULL;
u8 index, vmargin_uv;
pboardobjgrp = &g->perf_pmu->volt.volt_rail_metadata.volt_rails.super;
pboardobjgrp = &g->pmu->volt->volt_rail_metadata.volt_rails.super;
BOARDOBJGRP_FOR_EACH(pboardobjgrp, struct boardobj *, pboardobj, index) {
volt_rail = (struct voltage_rail *)(void *)pboardobj;

2
drivers/gpu/nvgpu/common/pmu/volt/volt_rail.h
View File

@@ -29,5 +29,7 @@
#define CTRL_PMGR_PWR_EQUATION_INDEX_INVALID 0xFFU
int nvgpu_volt_rail_sw_setup(struct gk20a *g);
int nvgpu_volt_rail_pmu_setup(struct gk20a *g);
#endif /* NVGPU_VOLT_RAIL_H */

5
drivers/gpu/nvgpu/hal/clk/clk_tu104.c
View File

@@ -334,6 +334,7 @@ int nvgpu_clk_mon_check_status(struct gk20a *g,
return 0;
}
#ifdef CONFIG_NVGPU_CLK_ARB
u32 tu104_crystal_clk_hz(struct gk20a *g)
{
return (XTAL4X_KHZ * 1000);
@@ -590,7 +591,6 @@ u32 tu104_get_rate_cntr(struct gk20a *g, struct namemap_cfg *c) {
return -EBUSY;
}
#ifdef CONFIG_NVGPU_CLK_ARB
int tu104_clk_domain_get_f_points(
struct gk20a *g,
u32 clkapidomain,
@@ -620,13 +620,12 @@ int tu104_clk_domain_get_f_points(
}
return status;
}
#endif
void tu104_suspend_clk_support(struct gk20a *g)
{
nvgpu_mutex_destroy(&g->clk.clk_mutex);
}
#ifdef CONFIG_NVGPU_CLK_ARB
unsigned long tu104_clk_maxrate(struct gk20a *g, u32 api_domain)
{
u16 min_mhz = 0, max_mhz = 0;

4
drivers/gpu/nvgpu/hal/init/hal_tu104.c
View File

@@ -1239,17 +1239,17 @@ static const struct gpu_ops tu104_ops = {
gm20b_clear_pmu_bar0_host_err_status,
},
.clk = {
#ifdef CONFIG_NVGPU_CLK_ARB
.init_clk_support = tu104_init_clk_support,
.get_crystal_clk_hz = tu104_crystal_clk_hz,
.get_rate_cntr = tu104_get_rate_cntr,
.measure_freq = tu104_clk_measure_freq,
.suspend_clk_support = tu104_suspend_clk_support,
.perf_pmu_vfe_load = nvgpu_perf_pmu_vfe_load_ps35,
#ifdef CONFIG_NVGPU_CLK_ARB
.clk_domain_get_f_points = tu104_clk_domain_get_f_points,
.get_maxrate = tu104_clk_maxrate,
.get_change_seq_time = tu104_get_change_seq_time,
#endif
.perf_pmu_vfe_load = nvgpu_perf_pmu_vfe_load_ps35,
.change_host_clk_source = tu104_change_host_clk_source,
.clk_mon_check_master_fault_status =
nvgpu_clk_mon_check_master_fault_status,

1
drivers/gpu/nvgpu/include/nvgpu/pmu.h
View File

@@ -302,6 +302,7 @@ struct nvgpu_pmu {
struct nvgpu_pmu_perfmon *pmu_perfmon;
struct nvgpu_clk_pmupstate *clk_pmu;
struct therm_pmupstate *therm_pmu;
struct nvgpu_pmu_volt *volt;
void (*remove_support)(struct nvgpu_pmu *pmu);
void (*volt_rpc_handler)(struct gk20a *g,

2
drivers/gpu/nvgpu/include/nvgpu/pmu/perf.h
View File

@@ -26,7 +26,6 @@
#include <nvgpu/cond.h>
#include <nvgpu/thread.h>
#include <nvgpu/pmu/perf_pstate.h>
#include <nvgpu/pmu/volt.h>
#include <nvgpu/pmu/lpwr.h>
#include <nvgpu/boardobjgrp_e32.h>
#include <nvgpu/boardobjgrp_e255.h>
@@ -87,7 +86,6 @@ struct perf_pmupstate {
struct vfe_vars vfe_varobjs;
struct vfe_equs vfe_equobjs;
struct pstates pstatesobjs;
struct obj_volt volt;
struct obj_lwpr lpwr;
struct nvgpu_vfe_invalidate vfe_init;
struct change_seq_pmu changeseq_pmu;

16
drivers/gpu/nvgpu/include/nvgpu/pmu/volt.h
View File

@@ -61,7 +61,7 @@ struct voltage_policy_metadata {
struct boardobjgrp_e32 volt_policies;
};
struct obj_volt {
struct nvgpu_pmu_volt {
struct voltage_rail_metadata volt_rail_metadata;
struct voltage_device_metadata volt_dev_metadata;
struct voltage_policy_metadata volt_policy_metadata;
@@ -90,16 +90,6 @@ struct voltage_rail {
u32 current_volt_uv;
};
int nvgpu_volt_send_load_cmd_to_pmu(struct gk20a *g);
int nvgpu_volt_dev_sw_setup(struct gk20a *g);
int nvgpu_volt_dev_pmu_setup(struct gk20a *g);
int nvgpu_volt_policy_sw_setup(struct gk20a *g);
int nvgpu_volt_policy_pmu_setup(struct gk20a *g);
int nvgpu_volt_rail_sw_setup(struct gk20a *g);
int nvgpu_volt_rail_pmu_setup(struct gk20a *g);
u8 nvgpu_volt_rail_volt_domain_convert_to_idx(struct gk20a *g, u8 volt_domain);
int nvgpu_volt_get_vmin_vmax_ps35(struct gk20a *g, u32 *vmin_uv, u32 *vmax_uv);
u8 nvgpu_volt_get_vmargin_ps35(struct gk20a *g);
@@ -109,5 +99,9 @@ u8 nvgpu_volt_rail_vbios_volt_domain_convert_to_internal
(struct gk20a *g, u8 vbios_volt_domain);
void nvgpu_pmu_volt_rpc_handler(struct gk20a *g, struct nv_pmu_rpc_header *rpc);
int nvgpu_volt_get_curr_volt_ps35(struct gk20a *g, u32 *vcurr_uv);
int nvgpu_pmu_volt_sw_setup(struct gk20a *g);
void nvgpu_pmu_volt_deinit(struct gk20a *g);
int nvgpu_pmu_volt_init(struct gk20a *g);
int nvgpu_pmu_volt_pmu_setup(struct gk20a *g);
#endif /* NVGPU_PMU_VOLT_H */