gpu: nvgpu: add gpu characteristics flag for reduced profile

Several of the nvgpu driver capabilities will be disabled in the reduced
version. To know the version of the nvgpu driver we introduce a new
global characteristic flag NVGPU_DRIVER_REDUCED_PROFILE.

JIRA NVGPU-3062

Change-Id: I93c76df1110c24ea0055c77d332fe297d56db65d
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2108143
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Sagar Kamble
2019-04-26 14:30:27 +05:30
committed by mobile promotions
parent fde780300d
commit 150e1ad3c9
4 changed files with 12 additions and 1 deletions

View File

@@ -528,6 +528,9 @@ int gk20a_wait_for_idle(struct gk20a *g)
void gk20a_init_gpu_characteristics(struct gk20a *g) void gk20a_init_gpu_characteristics(struct gk20a *g)
{ {
#ifdef NVGPU_REDUCED
nvgpu_set_enabled(g, NVGPU_DRIVER_REDUCED_PROFILE, true);
#endif
nvgpu_set_enabled(g, NVGPU_SUPPORT_MAP_DIRECT_KIND_CTRL, true); nvgpu_set_enabled(g, NVGPU_SUPPORT_MAP_DIRECT_KIND_CTRL, true);
nvgpu_set_enabled(g, NVGPU_SUPPORT_MAP_BUFFER_BATCH, true); nvgpu_set_enabled(g, NVGPU_SUPPORT_MAP_BUFFER_BATCH, true);
nvgpu_set_enabled(g, NVGPU_SUPPORT_SPARSE_ALLOCS, true); nvgpu_set_enabled(g, NVGPU_SUPPORT_SPARSE_ALLOCS, true);

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@@ -196,10 +196,14 @@ struct gk20a;
/* PMU Super surface */ /* PMU Super surface */
#define NVGPU_SUPPORT_PMU_SUPER_SURFACE 76 #define NVGPU_SUPPORT_PMU_SUPER_SURFACE 76
/* Reduced profile of nvgpu driver */
#define NVGPU_DRIVER_REDUCED_PROFILE 77
/* /*
* Must be greater than the largest bit offset in the above list. * Must be greater than the largest bit offset in the above list.
*/ */
#define NVGPU_MAX_ENABLED_BITS 77U #define NVGPU_MAX_ENABLED_BITS 78U
/** /**
* nvgpu_is_enabled - Check if the passed flag is enabled. * nvgpu_is_enabled - Check if the passed flag is enabled.

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@@ -234,6 +234,8 @@ static struct nvgpu_flags_mapping flags_mapping[] = {
NVGPU_SUPPORT_SCG}, NVGPU_SUPPORT_SCG},
{NVGPU_GPU_FLAGS_SUPPORT_VPR, {NVGPU_GPU_FLAGS_SUPPORT_VPR,
NVGPU_SUPPORT_VPR}, NVGPU_SUPPORT_VPR},
{NVGPU_GPU_FLAGS_DRIVER_REDUCED_PROFILE,
NVGPU_DRIVER_REDUCED_PROFILE},
}; };
static u64 nvgpu_ctrl_ioctl_gpu_characteristics_flags(struct gk20a *g) static u64 nvgpu_ctrl_ioctl_gpu_characteristics_flags(struct gk20a *g)

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@@ -166,6 +166,8 @@ struct nvgpu_gpu_zbc_query_table_args {
#define NVGPU_GPU_FLAGS_CAN_RAILGATE (1ULL << 29) #define NVGPU_GPU_FLAGS_CAN_RAILGATE (1ULL << 29)
/* Usermode submit is available */ /* Usermode submit is available */
#define NVGPU_GPU_FLAGS_SUPPORT_USERMODE_SUBMIT (1ULL << 30) #define NVGPU_GPU_FLAGS_SUPPORT_USERMODE_SUBMIT (1ULL << 30)
/* Reduced profile is enabled */
#define NVGPU_GPU_FLAGS_DRIVER_REDUCED_PROFILE (1ULL << 31)
/* SM LRF ECC is enabled */ /* SM LRF ECC is enabled */
#define NVGPU_GPU_FLAGS_ECC_ENABLED_SM_LRF (1ULL << 60) #define NVGPU_GPU_FLAGS_ECC_ENABLED_SM_LRF (1ULL << 60)
/* SM SHM ECC is enabled */ /* SM SHM ECC is enabled */