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gpu: nvgpu: Fix for pes_tpc_mask programming

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After CONFIG_UBSAN kernel compilation flag to know any shifting
cause overflow or not enablement ,this is identified.
The register "gr_fe_tpc_fs_r(gpc_index)" is read only after
Volta. The gops where we are computing the index is not needed.

Bug 200727116

Change-Id: Ib2306103389ba9df77fd59d012ec70e775104989
Signed-off-by: dt <dt@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2573296
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
dt
2021-08-09 18:20:53 +00:00
committed by mobile promotions
parent 4034de5756
commit 152d7c9edd
12 changed files with 78 additions and 70 deletions
Download Patch File Download Diff File Expand all files Collapse all files

62
drivers/gpu/nvgpu/common/gr/fs_state.c
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@@ -49,64 +49,6 @@ static int gr_load_sm_id_config(struct gk20a *g, struct nvgpu_gr_config *config)
return err;
}
static void gr_load_tpc_mask(struct gk20a *g, struct nvgpu_gr_config *config)
{
u32 pes_tpc_mask = 0;
u32 gpc, pes;
u32 num_tpc_per_gpc = nvgpu_get_litter_value(g,
GPU_LIT_NUM_TPC_PER_GPC);
#ifdef CONFIG_NVGPU_NON_FUSA
u32 max_tpc_count = nvgpu_gr_config_get_max_tpc_count(config);
u32 fuse_tpc_mask;
u32 val;
u32 cur_gr_instance = nvgpu_gr_get_cur_instance_id(g);
u32 gpc_phys_id;
#endif
/* gv11b has 1 GPC and 4 TPC/GPC, so mask will not overflow u32 */
for (gpc = 0; gpc < nvgpu_gr_config_get_gpc_count(config); gpc++) {
for (pes = 0;
pes < nvgpu_gr_config_get_pe_count_per_gpc(config);
pes++) {
pes_tpc_mask |= nvgpu_gr_config_get_pes_tpc_mask(
config, gpc, pes) <<
nvgpu_safe_mult_u32(num_tpc_per_gpc, gpc);
}
}
nvgpu_log_info(g, "pes_tpc_mask %u\n", pes_tpc_mask);
#ifdef CONFIG_NVGPU_NON_FUSA
if (!nvgpu_is_enabled(g, NVGPU_SUPPORT_MIG)) {
/*
* Fuse registers must be queried with physical gpc-id and not
* the logical ones. For tu104 and before chips logical gpc-id
* is same as physical gpc-id for non-floorswept config but for
* chips after tu104 it may not be true.
*/
gpc_phys_id = nvgpu_grmgr_get_gr_gpc_phys_id(g,
cur_gr_instance, 0U);
fuse_tpc_mask = g->ops.gr.config.get_gpc_tpc_mask(g, config, gpc_phys_id);
if ((g->tpc_fs_mask_user != 0U) &&
(g->tpc_fs_mask_user != fuse_tpc_mask)) {
if (fuse_tpc_mask == nvgpu_safe_sub_u32(BIT32(max_tpc_count),
U32(1))) {
val = g->tpc_fs_mask_user;
val &= nvgpu_safe_sub_u32(BIT32(max_tpc_count), U32(1));
/*
* skip tpc to disable the other tpc cause channel
* timeout
*/
val = nvgpu_safe_sub_u32(BIT32(hweight32(val)), U32(1));
pes_tpc_mask = val;
}
}
}
#endif
g->ops.gr.init.tpc_mask(g, 0, pes_tpc_mask);
}
int nvgpu_gr_fs_state_init(struct gk20a *g, struct nvgpu_gr_config *config)
{
u32 tpc_index, gpc_index;
@@ -184,7 +126,9 @@ int nvgpu_gr_fs_state_init(struct gk20a *g, struct nvgpu_gr_config *config)
g->ops.gr.init.cwd_gpcs_tpcs_num(g, gpc_cnt, tpc_cnt);
gr_load_tpc_mask(g, config);
if (g->ops.gr.init.gr_load_tpc_mask != NULL) {
g->ops.gr.init.gr_load_tpc_mask(g, config);
}
err = gr_load_sm_id_config(g, config);
if (err != 0) {