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gpu: nvgpu: Fix for smid programming

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As number of available tpc/gpc is more than 4 in new dgpu,
this fix is needed for correct sm_id config programming.

After CONFIG_UBSAN kernel compilation flag to know any shifting
cause overflow or not enablement , this is identified where the
shift is overflowing u32 when number of available TPCs is more
than four.

Bug 200727116

Change-Id: I9169a00614e4a648afe4a2d2f8e76c178e8c19eb
Signed-off-by: dt <dt@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2571823
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
This commit is contained in:
dt
2021-08-06 09:55:16 +00:00
committed by mobile promotions
parent 9355345610
commit 4034de5756
1 changed files with 1 additions and 1 deletions
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2
drivers/gpu/nvgpu/hal/gr/init/gr_init_gv11b_fusa.c
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@@ -510,7 +510,7 @@ int gv11b_gr_init_sm_id_config(struct gk20a *g, u32 *tpc_sm_id,
index = nvgpu_safe_add_u32(gpc_index, index);
tpc_sm_id[index] |= (tpc_id <<
nvgpu_safe_mult_u32(
tpc_index,
(tpc_index & 3U),
bit_stride));
}
nvgpu_gr_ctx_patch_write(g, gr_ctx,