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gpu: nvgpu: Fix MISRA 10.6 violations in nvlink

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MISRA rule 10.6 does not allow assigning of composite expression
to an object with wider essential type. Fix 10.6 violations in nvlink
code by changing the data-type or by type-casting.

JIRA NVGPU-1921

Change-Id: I2d661ca7960e49ebc062c4eb8817004f73297cf5
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2022881
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Tejal Kudav
2019-02-19 11:45:50 +05:30
committed by mobile promotions
parent ccc0f39f40
commit 153daf7adf
2 changed files with 3 additions and 2 deletions
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3
drivers/gpu/nvgpu/common/nvlink/intr_and_err_handling_gv100.c
View File

@@ -253,7 +253,8 @@ static void gv100_nvlink_minion_isr(struct gk20a *g) {
minion_minion_intr_nonfatal_f(1)); minion_minion_intr_nonfatal_f(1));
} }
links = minion_minion_intr_link_v(intr) & g->nvlink.enabled_links; links = minion_minion_intr_link_v(intr) &
(unsigned long) g->nvlink.enabled_links;
if (links != 0UL) { if (links != 0UL) {
for_each_set_bit(bit, &links, NVLINK_MAX_LINKS_SW) { for_each_set_bit(bit, &links, NVLINK_MAX_LINKS_SW) {

2
drivers/gpu/nvgpu/common/nvlink/nvlink_gv100.c
View File

@@ -507,7 +507,7 @@ int gv100_nvlink_setup_pll(struct gk20a *g, unsigned long link_mask)
struct nvgpu_timeout timeout; struct nvgpu_timeout timeout;
u32 pad_ctrl = 0U; u32 pad_ctrl = 0U;
u32 swap_ctrl = 0U; u32 swap_ctrl = 0U;
u32 pll_id; u8 pll_id;
unsigned long bit; unsigned long bit;
reg = gk20a_readl(g, trim_sys_nvlink_uphy_cfg_r()); reg = gk20a_readl(g, trim_sys_nvlink_uphy_cfg_r());