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gpu: nvgpu: nvgpu_memcpy changes to pmu code

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MISRA Rule 21.15 prohibits use of memcpy() with incompatible ptrs
to qualified/unqualified types.

To circumvent this issue we've introduced a new MISRA-compliant
nvgpu_memcpy() function.

This change switches non-offending memcpy usage in pmu/* code
over to to use nvgpu_memcpy() with appropriate casts applied
to maintain consistency within nvgpu.

JIRA NVGPU-849

Change-Id: I095abe3a95071d619ed1cf8421150139a7d4ab93
Signed-off-by: Scott Long <scottl@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1946263
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Scott Long
2018-11-08 20:16:29 -08:00
committed by mobile promotions
parent 99e9cdb2e7
commit 170b46f851
3 changed files with 9 additions and 5 deletions
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4
drivers/gpu/nvgpu/common/pmu/pmu.c
View File

@@ -30,6 +30,7 @@
#include <nvgpu/bug.h>
#include <nvgpu/utils.h>
#include <nvgpu/gk20a.h>
#include <nvgpu/string.h>
static int nvgpu_pg_init_task(void *arg);
@@ -411,7 +412,8 @@ int nvgpu_pmu_process_init_msg(struct nvgpu_pmu *pmu,
BUG_ON(sizeof(pmu->gid_info.gid) !=
sizeof(gid_data.gid));
(void) memcpy(pmu->gid_info.gid, gid_data.gid,
nvgpu_memcpy((u8 *)pmu->gid_info.gid,
(u8 *)gid_data.gid,
sizeof(pmu->gid_info.gid));
}
}

3
drivers/gpu/nvgpu/common/pmu/pmu_ipc.c
View File

@@ -528,7 +528,8 @@ static int pmu_response_handle(struct nvgpu_pmu *pmu,
} else if (seq->state != PMU_SEQ_STATE_CANCELLED) {
if (seq->msg != NULL) {
if (seq->msg->hdr.size >= msg->hdr.size) {
(void) memcpy(seq->msg, msg, msg->hdr.size);
nvgpu_memcpy((u8 *)seq->msg, (u8 *)msg,
msg->hdr.size);
} else {
nvgpu_err(g, "sequence %d msg buffer too small",
seq->id);

7
drivers/gpu/nvgpu/common/pmu/pmu_pg.c
View File

@@ -27,6 +27,7 @@
#include <nvgpu/bug.h>
#include <nvgpu/utils.h>
#include <nvgpu/gk20a.h>
#include <nvgpu/string.h>
/* state transition :
* OFF => [OFF_ON_PENDING optional] => ON_PENDING => ON => OFF
@@ -685,9 +686,9 @@ int nvgpu_pmu_ap_send_command(struct gk20a *g,
nvgpu_pmu_dbg(g, "cmd post PMU_AP_CMD_ID_INIT_AND_ENABLE_CTRL");
cmd.cmd.pg.ap_cmd.init_and_enable_ctrl.ctrl_id =
p_ap_cmd->init_and_enable_ctrl.ctrl_id;
(void) memcpy(
(void *)&(cmd.cmd.pg.ap_cmd.init_and_enable_ctrl.params),
(void *)&(p_ap_cmd->init_and_enable_ctrl.params),
nvgpu_memcpy(
(u8 *)&(cmd.cmd.pg.ap_cmd.init_and_enable_ctrl.params),
(u8 *)&(p_ap_cmd->init_and_enable_ctrl.params),
sizeof(struct pmu_ap_ctrl_init_params));
p_callback = ap_callback_init_and_enable_ctrl;