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gpu: nvgpu: move nvgpu_gr_wait_initialized to hal

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Move nvgpu_gr_wait_initialized to a gr.init hal function.
Move to hal function to avoid circular dependencies of headers.

Update nvgpu_gr_wait_initialized call to
g->ops.gr.init.wait_initialized

JIRA NVGPU-3016

Change-Id: Ia2e5f78da8528c76a8d08512151483579f250676
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2085740
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Vinod G
2019-03-30 09:44:49 -07:00
committed by mobile promotions
parent 6177eacc71
commit 1819c36562
10 changed files with 26 additions and 19 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
drivers/gpu/nvgpu/common/pmu/pg/pmu_pg.c
View File

@@ -29,7 +29,6 @@
#include <nvgpu/gk20a.h>
#include <nvgpu/string.h>
#include <nvgpu/engines.h>
#include <nvgpu/gr/gr.h>
/* state transition :
* OFF => [OFF_ON_PENDING optional] => ON_PENDING => ON => OFF
@@ -536,7 +535,7 @@ int nvgpu_pmu_init_powergating(struct gk20a *g)
pg_engine_id_list = g->ops.pmu.pmu_pg_supported_engines_list(g);
}
nvgpu_gr_wait_initialized(g);
g->ops.gr.init.wait_initialized(g);
for (pg_engine_id = PMU_PG_ELPG_ENGINE_ID_GRAPHICS;
pg_engine_id < PMU_PG_ELPG_ENGINE_ID_INVALID_ENGINE;

19
drivers/gpu/nvgpu/common/power_features/cg/cg.c
View File

@@ -21,7 +21,6 @@
*/
#include <nvgpu/gk20a.h>
#include <nvgpu/gr/gr.h>
#include <nvgpu/enabled.h>
#include <nvgpu/power_features/cg.h>
@@ -94,7 +93,7 @@ void nvgpu_cg_elcg_enable(struct gk20a *g)
return;
}
nvgpu_gr_wait_initialized(g);
g->ops.gr.init.wait_initialized(g);
nvgpu_mutex_acquire(&g->cg_pg_lock);
if (g->elcg_enabled) {
@@ -111,7 +110,7 @@ void nvgpu_cg_elcg_disable(struct gk20a *g)
return;
}
nvgpu_gr_wait_initialized(g);
g->ops.gr.init.wait_initialized(g);
nvgpu_mutex_acquire(&g->cg_pg_lock);
if (g->elcg_enabled) {
@@ -129,7 +128,7 @@ void nvgpu_cg_blcg_mode_enable(struct gk20a *g)
return;
}
nvgpu_gr_wait_initialized(g);
g->ops.gr.init.wait_initialized(g);
nvgpu_mutex_acquire(&g->cg_pg_lock);
if (g->blcg_enabled) {
@@ -147,7 +146,7 @@ void nvgpu_cg_blcg_mode_disable(struct gk20a *g)
return;
}
nvgpu_gr_wait_initialized(g);
g->ops.gr.init.wait_initialized(g);
nvgpu_mutex_acquire(&g->cg_pg_lock);
if (g->blcg_enabled) {
@@ -305,7 +304,7 @@ void nvgpu_cg_slcg_gr_perf_ltc_load_enable(struct gk20a *g)
return;
}
nvgpu_gr_wait_initialized(g);
g->ops.gr.init.wait_initialized(g);
nvgpu_mutex_acquire(&g->cg_pg_lock);
if (!g->slcg_enabled) {
@@ -332,7 +331,7 @@ void nvgpu_cg_slcg_gr_perf_ltc_load_disable(struct gk20a *g)
return;
}
nvgpu_gr_wait_initialized(g);
g->ops.gr.init.wait_initialized(g);
nvgpu_mutex_acquire(&g->cg_pg_lock);
if (!g->slcg_enabled) {
@@ -476,7 +475,7 @@ void nvgpu_cg_elcg_set_elcg_enabled(struct gk20a *g, bool enable)
return;
}
nvgpu_gr_wait_initialized(g);
g->ops.gr.init.wait_initialized(g);
nvgpu_mutex_release(&g->cg_pg_lock);
if (enable) {
@@ -503,7 +502,7 @@ void nvgpu_cg_blcg_set_blcg_enabled(struct gk20a *g, bool enable)
return;
}
nvgpu_gr_wait_initialized(g);
g->ops.gr.init.wait_initialized(g);
nvgpu_mutex_acquire(&g->cg_pg_lock);
if (enable) {
@@ -564,7 +563,7 @@ void nvgpu_cg_slcg_set_slcg_enabled(struct gk20a *g, bool enable)
return;
}
nvgpu_gr_wait_initialized(g);
g->ops.gr.init.wait_initialized(g);
nvgpu_mutex_acquire(&g->cg_pg_lock);
if (enable) {

7
drivers/gpu/nvgpu/common/power_features/pg/pg.c
View File

@@ -21,7 +21,6 @@
*/
#include <nvgpu/gk20a.h>
#include <nvgpu/gr/gr.h>
#include <nvgpu/pmu.h>
#include <nvgpu/power_features/pg.h>
@@ -47,7 +46,7 @@ int nvgpu_pg_elpg_enable(struct gk20a *g)
return 0;
}
nvgpu_gr_wait_initialized(g);
g->ops.gr.init.wait_initialized(g);
nvgpu_mutex_acquire(&g->cg_pg_lock);
if (g->elpg_enabled) {
@@ -67,7 +66,7 @@ int nvgpu_pg_elpg_disable(struct gk20a *g)
return 0;
}
nvgpu_gr_wait_initialized(g);
g->ops.gr.init.wait_initialized(g);
nvgpu_mutex_acquire(&g->cg_pg_lock);
if (g->elpg_enabled) {
@@ -88,7 +87,7 @@ int nvgpu_pg_elpg_set_elpg_enabled(struct gk20a *g, bool enable)
return 0;
}
nvgpu_gr_wait_initialized(g);
g->ops.gr.init.wait_initialized(g);
nvgpu_mutex_acquire(&g->cg_pg_lock);
if (enable) {

5
drivers/gpu/nvgpu/common/power_features/power_features.c
View File

@@ -21,7 +21,6 @@
*/
#include <nvgpu/gk20a.h>
#include <nvgpu/gr/gr.h>
#include <nvgpu/power_features/cg.h>
#include <nvgpu/power_features/pg.h>
#include <nvgpu/power_features/power_features.h>
@@ -32,7 +31,7 @@ int nvgpu_cg_pg_disable(struct gk20a *g)
nvgpu_log_fn(g, " ");
nvgpu_gr_wait_initialized(g);
g->ops.gr.init.wait_initialized(g);
/* disable elpg before clock gating */
err = nvgpu_pg_elpg_disable(g);
@@ -54,7 +53,7 @@ int nvgpu_cg_pg_enable(struct gk20a *g)
nvgpu_log_fn(g, " ");
nvgpu_gr_wait_initialized(g);
g->ops.gr.init.wait_initialized(g);
nvgpu_cg_elcg_enable(g);

2
drivers/gpu/nvgpu/gm20b/hal_gm20b.c
View File

@@ -38,6 +38,7 @@
#include <nvgpu/regops.h>
#include <nvgpu/gr/zbc.h>
#include <nvgpu/gr/zcull.h>
#include <nvgpu/gr/gr.h>
#include <nvgpu/gr/gr_falcon.h>
#include <nvgpu/gr/setup.h>
@@ -411,6 +412,7 @@ static const struct gpu_ops gm20b_ops = {
.program_zcull_mapping = gm20b_gr_program_zcull_mapping,
},
.init = {
.wait_initialized = nvgpu_gr_wait_initialized,
.ecc_scrub_reg = NULL,
.get_fbp_en_mask = gm20b_gr_init_get_fbp_en_mask,
.lg_coalesce = gm20b_gr_init_lg_coalesce,

2
drivers/gpu/nvgpu/gp10b/hal_gp10b.c
View File

@@ -41,6 +41,7 @@
#include <nvgpu/gr/gr_falcon.h>
#include <nvgpu/gr/setup.h>
#include <nvgpu/gr/fecs_trace.h>
#include <nvgpu/gr/gr.h>
#include "hal/mc/mc_gm20b.h"
#include "hal/mc/mc_gp10b.h"
@@ -481,6 +482,7 @@ static const struct gpu_ops gp10b_ops = {
.program_zcull_mapping = gm20b_gr_program_zcull_mapping,
},
.init = {
.wait_initialized = nvgpu_gr_wait_initialized,
.ecc_scrub_reg = NULL,
.get_fbp_en_mask = gm20b_gr_init_get_fbp_en_mask,
.lg_coalesce = gm20b_gr_init_lg_coalesce,

2
drivers/gpu/nvgpu/gv100/hal_gv100.c
View File

@@ -170,6 +170,7 @@
#include <nvgpu/gr/gr_falcon.h>
#include <nvgpu/gr/setup.h>
#include <nvgpu/gr/fecs_trace.h>
#include <nvgpu/gr/gr.h>
#include <nvgpu/hw/gv100/hw_proj_gv100.h>
#include <nvgpu/hw/gv100/hw_top_gv100.h>
@@ -622,6 +623,7 @@ static const struct gpu_ops gv100_ops = {
gv100_gr_hwpm_map_get_active_fbpa_mask,
},
.init = {
.wait_initialized = nvgpu_gr_wait_initialized,
.ecc_scrub_reg = NULL,
.get_fbp_en_mask = gm20b_gr_init_get_fbp_en_mask,
.lg_coalesce = gm20b_gr_init_lg_coalesce,

2
drivers/gpu/nvgpu/gv11b/hal_gv11b.c
View File

@@ -145,6 +145,7 @@
#include <nvgpu/gr/zcull.h>
#include <nvgpu/gr/setup.h>
#include <nvgpu/gr/fecs_trace.h>
#include <nvgpu/gr/gr.h>
#include <nvgpu/hw/gv11b/hw_proj_gv11b.h>
#include <nvgpu/hw/gv11b/hw_top_gv11b.h>
@@ -580,6 +581,7 @@ static const struct gpu_ops gv11b_ops = {
gv100_gr_hwpm_map_align_regs_perf_pma,
},
.init = {
.wait_initialized = nvgpu_gr_wait_initialized,
.ecc_scrub_reg = gv11b_gr_init_ecc_scrub_reg,
.get_fbp_en_mask = gm20b_gr_init_get_fbp_en_mask,
.lg_coalesce = gm20b_gr_init_lg_coalesce,

1
drivers/gpu/nvgpu/include/nvgpu/gk20a.h
View File

@@ -680,6 +680,7 @@ struct gpu_ops {
} hwpm_map;
struct {
void (*wait_initialized)(struct gk20a *g);
void (*ecc_scrub_reg)(struct gk20a *g,
struct nvgpu_gr_config *gr_config);
u32 (*get_fbp_en_mask)(struct gk20a *g);

2
drivers/gpu/nvgpu/tu104/hal_tu104.c
View File

@@ -189,6 +189,7 @@
#include <nvgpu/gr/fecs_trace.h>
#include <nvgpu/pmu/perf.h>
#include <nvgpu/gr/gr_falcon.h>
#include <nvgpu/gr/gr.h>
#include <nvgpu/hw/tu104/hw_proj_tu104.h>
#include <nvgpu/hw/tu104/hw_top_tu104.h>
@@ -650,6 +651,7 @@ static const struct gpu_ops tu104_ops = {
gv100_gr_hwpm_map_get_active_fbpa_mask,
},
.init = {
.wait_initialized = nvgpu_gr_wait_initialized,
.ecc_scrub_reg = NULL,
.get_fbp_en_mask = gm20b_gr_init_get_fbp_en_mask,
.lg_coalesce = gm20b_gr_init_lg_coalesce,